Datasheet > GS8672Q38BGE-400

GS8672Q38BGE-400

更新时间： 2024-11-20 00:36:35

品牌	Logo	应用领域
GSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	457K
描述
On-Chip ECC with virtually zero SER

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS8672Q38BGE-400 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
Factory Lead Time：	12 weeks	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	400 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	75497472 bit	内存集成电路类型：	QDR SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.5,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	1.86 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

GS8672Q38BGE-400 数据手册

GS8672Q20/38BE-500/450/400

72Mb SigmaQuad-II+^TM

Burst of 2 ECCRAM^TM

500 MHz–400 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.5 Clock Latency

The GS8672Q20/38BE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 36Mb and144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Each internal read and write operation in a SigmaQuad-II+ B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B2 ECCRAM is always one address

pin less than the advertised index depth (e.g., the 4M x18 has

an 2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

SigmaQuad™ ECCRAM Overview

The GS8672Q20/38BE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672Q20/38BE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.01c 8/2017

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

中文翻译

下载PDF

与GS8672Q38BGE-400相关器件

型号	品牌	获取价格	描述	数据表
GS8672Q38BGE-400I	GSI	获取价格	On-Chip ECC with virtually zero SER
GS8672Q38BGE-400IT	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q38BGE-400T	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q38BGE-450	GSI	获取价格	On-Chip ECC with virtually zero SER
GS8672Q38BGE-450I	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q38BGE-500	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q38BGE-500I	GSI	获取价格	On-Chip ECC with virtually zero SER
GS8672Q38BGE-500T	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672T18AE-200	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
GS8672T18AE-250	GSI	获取价格	DDR SRAM, 4MX18, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165

与GS8672Q38BGE-400相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

44

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672Q38BGE-400

GS8672Q38BGE-400 技术参数

GS8672Q38BGE-400 数据手册

与GS8672Q38BGE-400相关器件

与GS8672Q38BGE-400相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672Q38BGE-400

GS8672Q38BGE-400 技术参数

GS8672Q38BGE-400 数据手册

与GS8672Q38BGE-400相关器件

与GS8672Q38BGE-400相关文章

您还可以找

您在本页遇到什么问题？