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GS8320E32AGT-150I PDF预览

GS8320E32AGT-150I

更新时间： 2024-11-05 14:33:43
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 352K
描述
Cache SRAM, 1MX32, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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GS8320E32AGT-150I 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：8 weeks风险等级：5.35
最长访问时间：7.5 ns其他特性：ALSO OPERATED WITH 2.5V SUPPLY; PIPELINE/FLOW THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：150 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：33554432 bit内存集成电路类型：CACHE SRAM
内存宽度：32功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：2.3 V
子类别：SRAMs最大压摆率：0.195 mA
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS8320E32AGT-150I 数据手册

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GS8320E18/32/36AGT-400/375/333/250/200/150  
400 MHz–150 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
2M x 18, 1M x 32, 1M x 36  
36Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Dual Cycle Deselect (DCD) operation  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JRoHS-compliant 100-lead TQFP package available  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
DCD Pipelined Reads  
The GS8320E18/32/36AGT is a DCD (Dual Cycle Deselect)  
pipelined synchronous SRAM. SCD (Single Cycle Deselect)  
versions are also available. DCD SRAMs pipeline disable  
commands to the same degree as read commands. DCD RAMs  
hold the deselect command for one full cycle and then begin  
turning off their outputs just after the second rising edge of  
clock.  
Functional Description  
Applications  
The GS8320E18/32/36AGT is a 37,748,736-bit high  
performance synchronous SRAM with a 2-bit burst address  
counter. Although of a type originally developed for Level 2  
Cache applications supporting high performance CPUs, the  
device now finds application in synchronous SRAM  
applications, ranging from DSP main store to networking chip  
set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS8320E18/32/36AGT operates on a 3.3 V or 2.5 V  
power supply. All input are 3.3 V and 2.5 V compatible.  
Separate output power (V  
) pins are used to decouple  
DDQ  
output noise from the internal circuits and are 3.3 V and 2.5 V  
compatible.  
Parameter Synopsis  
-400  
-375  
-333  
-250  
-200  
-150  
Unit  
t
2.5  
2.5  
2.5  
2.66  
2.5  
3.3  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
395  
475  
390  
455  
355  
415  
280  
335  
240  
280  
205  
230  
mA  
mA  
t
4.0  
4.0  
4.2  
4.2  
4.5  
4.5  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
290  
335  
275  
320  
260  
305  
235  
270  
200  
240  
190  
220  
mA  
mA  
Rev: 1.03 8/2013  
1/23  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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与GS8320E32AGT-150I相关器件

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GS8320E32AGT-150IT GSI

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 		Cache SRAM, 1MX32, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E32AGT-150IV GSI

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GS8320E32AGT-150V GSI

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GS8320E32AGT-200 GSI

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GS8320E32AGT-200I GSI

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GS8320E32AGT-200IV GSI

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 		100 TQFP
GS8320E32AGT-200V GSI

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GS8320E32AGT-250 GSI

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 		100 TQFP
GS8320E32AGT-250I GSI

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 		Cache SRAM, 1MX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E32AGT-250IT GSI

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 		Cache SRAM, 1MX32, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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