Datasheet > GS8320E32AGT-333IVT

GS8320E32AGT-333IVT

更新时间： 2024-11-07 07:20:11

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
22页	331K
描述
SRAM

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GS8320E32AGT-333IVT 数据手册

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GS8320E18/32/36AGT-xxxV

333 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Dual Cycle Deselect (SDCD) operation

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

DCD Pipelined Reads

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• RoHS-compliant 100-lead TQFP package available

The GS8320E18/32/36AGT-xxxV is a DCD (Dual Cycle

Deselect) pipelined synchronous SRAM. SCD (Single Cycle

Deselect) versions are also available. DCD SRAMs pipeline

disable commands to the same degree as read commands. DCD

RAMs hold the deselect command for one full cycle and then

begin turning off their outputs just after the second rising edge

of clock.

Functional Description

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS8320E18/32/36AGT-xxxV is a 37,748,736-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

Core and Interface Voltages

The GS8320E18/32/36AGT-xxxV operates on a 1.8 V or 2.5 V

power supply. All inputs are 1.8 V or 2.5 V compatible.

Separate output power (V

) pins are used to decouple

DDQ

output noise from the internal circuits and are 1.8 V or 2.5 V

compatible.

Parameter Synopsis

-333

-250

-200

-150

Unit

3.0

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

365

425

290

345

250

290

215

240

5.0

5.5

6.5

7.5

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

270

315

245

280

210

250

200

230

Rev: 1.03 8/2013

1/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...22

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与GS8320E32AGT-333IVT相关器件

型号	品牌	获取价格	描述	数据表
GS8320E32AGT-333V	GSI	获取价格	100 TQFP
GS8320E32AGT-375	GSI	获取价格	100 TQFP
GS8320E32AGT-375I	GSI	获取价格	100 TQFP
GS8320E32AGT-400	GSI	获取价格	100 TQFP
GS8320E32AGT-400I	GSI	获取价格	100 TQFP
GS8320E32GT-133	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320E32GT-133I	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS8320E32GT-133IT	GSI	获取价格	Cache SRAM, 1MX32, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8320E32GT-133IV	GSI	获取价格	暂无描述
GS8320E32GT-133IVT	GSI	获取价格	Cache SRAM, 1MX32, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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