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GS82032T-138 PDF预览

GS82032T-138

更新时间： 2024-11-12 20:34:39
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 760K
描述
Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, TQFP-100

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GS82032T-138 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.89
最长访问时间：9.7 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：138 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：2097152 bit
内存集成电路类型：CACHE SRAM内存宽度：32
湿度敏感等级：3功能数量：1
端子数量：100字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.01 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.245 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS82032T-138 数据手册

 浏览型号GS82032T-138的Datasheet PDF文件第2页浏览型号GS82032T-138的Datasheet PDF文件第3页浏览型号GS82032T-138的Datasheet PDF文件第4页浏览型号GS82032T-138的Datasheet PDF文件第5页浏览型号GS82032T-138的Datasheet PDF文件第6页浏览型号GS82032T-138的Datasheet PDF文件第7页 
Preliminary  
GS82032T/Q-150/138/133/117/100/66  
150 MHz–66 MHz  
9 ns–18 ns  
TQFP, QFP  
Commercial Temp  
Industrial Temp  
64K x 32  
2M Synchronous Burst SRAM  
Flow Through/Pipeline Reads  
3.3 V V  
DD  
3.3 V and 2.5 V I/O  
Features  
The function of the Data Output register can be controlled by  
the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump  
1F in the FP-BGA). Holding the FT mode pin/bump low,  
places the RAM in Flow Through mode, causing output data to  
bypass the Data Output Register. Holding FT high places the  
RAM in Pipeline mode, activating the rising-edge-triggered  
Data Output Register.  
• FT pin for user-configurable flow through or pipeline  
operation  
• Single Cycle Deselect (SCD) operation  
• 3.3 V +10%/–5% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
SCD Pipelined Reads  
• Byte Write (BW) and/or Global Write (GW) operation  
• Common data inputs and data outputs  
• Clock Control, registered, address, data, and control  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP or QFP package  
The GS82032 is an SCD (Single Cycle Deselect) pipelined  
synchronous SRAM. DCD (Dual Cycle Deselect) versions are  
also available. SCD SRAMs pipeline deselect commands one  
stage less than read commands. SCD RAMs begin turning off  
their outputs immediately after the deselect command has been  
captured in the input registers.  
Byte Write and Global Write  
-150 -138 -133 -117 -100 -66 Unit  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the byte write  
control inputs.  
Pipeline tCycle 6.6 7.25 7.5 8.5  
10 12.5 ns  
ns  
270 245 240 210 180 150 mA  
3-1-1-1  
tKQ  
IDD  
3.8  
4
4
4.5  
5
6
Flow tCycle 10.5 15  
Through tKQ 9.7  
2-1-1-1  
15  
10  
15  
11  
15  
12  
20  
18  
ns  
ns  
9
Sleep Mode  
IDD  
170 120 120 120 120 95  
mA  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Functional Description  
Applications  
The GS82032 is a 2,097,152-bit high performance  
synchronous SRAM with a 2-bit burst address counter.  
Although of a type originally developed for Level 2 Cache  
applications supporting high performance CPUs, the device  
now finds application in synchronous SRAM applications  
ranging from DSP main store to networking chip set support.  
Core and Interface Voltages  
The GS82032 operates on a 3.3 V power supply and all inputs/  
outputs are 3.3 V- and 2.5 V-compatible. Separate output  
power (VDDQ) pins are used to decouple output noise from the  
internal circuit.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Rev: 1.04 2/2001  
1/23  
© 2000, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).  
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 		Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, TQFP-100
GS82032T-138IT GSI

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 		Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, TQFP-100
GS82032T-150 ETC

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GS82032T-150I ETC

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GS82032T-150T GSI

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 		Cache SRAM, 64KX32, 9ns, CMOS, PQFP100, TQFP-100
GS82032T-4 GSI

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 		Cache SRAM, 64KX32, 11ns, CMOS, PQFP100, TQFP-100
GS82032T-4I ETC

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 		64K x 32 2M Synchronous Burst SRAM
GS82032T-4IT GSI

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 		Cache SRAM, 64KX32, 11ns, CMOS, PQFP100, TQFP-100
GS82032T-5 GSI

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 		Cache SRAM, 64KX32, 12ns, CMOS, PQFP100, TQFP-100
GS82032T-5I ETC

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 		64K x 32 2M Synchronous Burst SRAM

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