Datasheet > GS820E32AGQ-150

GS820E32AGQ-150

更新时间： 2024-11-13 03:09:55

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
23页	344K
描述
Cache SRAM, 64KX32, 9ns, CMOS, PQFP100, QFP-100

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技术参数
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GS820E32AGQ-150 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	9 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	2097152 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	3.35 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	PURE MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS820E32AGQ-150 数据手册

GS820E32AT/Q-150/138/133/117/100/66

150Mhz - 66Mhz

9ns - 18ns

3.3V VDD

3.3V & 2.5V I/O

TQFP, QFP

Commercial Temp

Industrial Temp

64K x 32

2M Synchronous Burst SRAM

Flow Through / Pipeline Reads

Features

The function of the Data Output register can be controlled by the user

via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-

BGA). Holding the FT mode pin/bump low, places the RAM in Flow

through mode, causing output data to bypass the Data Output

activating the rising edge triggered Data Output Register.

• FT pin for user configurable flow through or pipelined operation.

• Dual Cycle Deselect (DCD) Operation.

• 3.3V +10%/-5% Core power supply

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Default to Interleaved Pipelined Mode.

DCD Pipelined Reads

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• JEDEC standard 100-lead TQFP or QFP package.

The GS820E32A is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are also

available. DCD SRAMs pipeline disable commands to the same

degree as read commands. DCD RAMs hold the deselect command

for one full cycle and then begin turning off their outputs just after the

second rising edge of clock.

Byte Write and Global Write

-150

Pipeline tCycle 6.6ns 7.25ns 7.5ns 8.5ns 10ns 12.5ns

3-1-1-1 3.8ns 4ns 4ns 4.5 5ns 6ns

IDD 270mA 245mA 240mA 210mA 180mA 150mA

Flow tCycle 10.5ns 15ns 15ns 15ns 15ns 20ns

Through tKQ 9ns 9.7ns 10ns 11ns 12ns 18ns

2-1-1-1 IDD 170mA 120mA 120mA 120mA 120mA 95mA

-138

-133

-117

-100

-66

Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In

addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

tKQ

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Functional Description

Core and Interface Voltages

The GS820E32A operates on a 3.3V power supply and all inputs/

outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)

pins are used to de-couple output noise from the internal circuit.

Applications

The GS820E32A is a 2,097,152 bit high performance synchronous

SRAM with a 2 bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPU’s, the device now finds application in synchronous

SRAM applications ranging from DSP main store to networking chip

set support.

Controls

Addresses, data I/O’s, chip enables (E¹, E2, E3), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive edge triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Rev: 1.04 3/2000

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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与GS820E32AGQ-150相关器件

型号	品牌	获取价格	描述	数据表
GS820E32AGQ-4	GSI	获取价格	Cache SRAM, 64KX32, 11ns, CMOS, PQFP100, QFP-100
GS820E32AGQ-5I	GSI	获取价格	Cache SRAM, 64KX32, 12ns, CMOS, PQFP100, QFP-100
GS820E32AGQ-5IT	GSI	获取价格	Cache SRAM, 64KX32, 12ns, CMOS, PQFP100, QFP-100
GS820E32AGQ-5T	GSI	获取价格	Cache SRAM, 64KX32, 12ns, CMOS, PQFP100, QFP-100
GS820E32AGQ-6I	GSI	获取价格	Cache SRAM, 64KX32, 18ns, CMOS, PQFP100, QFP-100
GS820E32AGT-133	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-133I	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-133IT	GSI	获取价格	Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS820E32AGT-133T	GSI	获取价格	Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS820E32AGT-138IT	GSI	获取价格	Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, TQFP-100

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