Datasheet > 存储 > SRAM> GS820E32AGT-133T

GS820E32AGT-133T

更新时间： 2024-11-12 13:07:59

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器
页数	文件大小	规格书
21页	549K
描述
Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, LEAD FREE, TQFP-100

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技术参数
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GS820E32AGT-133T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	10 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	2097152 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	PURE MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS820E32AGT-133T 数据手册

GS820E32AT-180/166/133/4/5

180 MHz–133 MHz

TQFP

Commercial Temp

Industrial Temp

64K x 32

2Mb Synchronous Burst SRAM

3.3 V V

3.3 V and 2.5 V I/O

counter may be configured to count in either linear or

Features

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• FT pin for user-configurable flow through or pipelined opera-

tion

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10%/–5% core power supply

Flow Through/Pipeline Reads

• 2.5 V or 3.3 V I/O supply

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14 in the TQFP). Holding

the FT mode pin low places the RAM in Flow Through mode,

causing output data to bypass the Data Output Register.

Holding FT high places the RAM in Pipelined mode,

activating the rising-edge-triggered Data Output Register.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

DCD Pipelined Reads

The GS820E32A is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are

also available. DCD SRAMs pipeline disable commands to the

same degree as read commands. DCD SRAMs hold the

deselect command for one full cycle and then begin turning off

their outputs just after the second rising edge of the clock.

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

Byte Write and Global Write

Applications

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

The GS820E32A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E¹, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Core and Interface Voltages

The GS820E32A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuit.

Rev: 1.07 10/2004

1/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...21

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与GS820E32AGT-133T相关器件

型号	品牌	获取价格	描述	数据表
GS820E32AGT-138IT	GSI	获取价格	Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, TQFP-100
GS820E32AGT-166	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-166I	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-166IT	GSI	获取价格	Cache SRAM, 64KX32, 8.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS820E32AGT-180	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-180I	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-180IT	GSI	获取价格	Cache SRAM, 64KX32, 8ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS820E32AGT-4	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-4I	GSI	获取价格	64K x 32 2Mb Synchronous Burst SRAM
GS820E32AGT-4IT	GSI	获取价格	Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, LEAD FREE, TQFP-100

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