Datasheet > GS8161Z36DGT-250IT

GS8161Z36DGT-250IT

更新时间： 2024-11-24 07:53:11

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
40页	546K
描述
ZBT SRAM, 512KX36, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D)

400 MHz–150 MHz

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V, 2.5 V, or 3.3 V V

1.8 V, 2.5 V, or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V, 2.5 V, or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and

144Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump BGA package

• RoHS-compliant 100-pin TQFP and 165-bump BGA

packages available

The GS8161Z18D(GT/D)/GS8161Z32D(D)/

GS8161Z36D(GT/D) may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising-edge-triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

Functional Description

The GS8161Z18D(GT/D)/GS8161Z32D(D)/

GS8161Z36D(GT/D) is an 18Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8161Z18D(GT/D)/GS8161Z32D(D)/

GS8161Z36D(GT/D) is implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 165-bump BGA package.

Parameter Synopsis

-400

-375

-333

-250

-200

-150

Unit

2.5

2.66

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

370

430

350

410

310

365

250

290

210

240

185

200

4.0

4.2

4.5

5.5

6.5

7.5

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

275

315

265

300

255

285

220

250

205

225

190

205

Rev: 1.03b 9/2013

1/40

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...40

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与GS8161Z36DGT-250IT相关器件

型号	品牌	获取价格	描述	数据表
GS8161Z36DGT-250IV	GSI	获取价格	100 TQFP
GS8161Z36DGT-250T	GSI	获取价格	ZBT SRAM, 512KX36, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DGT-250V	GSI	获取价格	100 TQFP
GS8161Z36DGT-333	GSI	获取价格	100 TQFP
GS8161Z36DGT-333I	GSI	获取价格	100 TQFP
GS8161Z36DGT-333ITFLASE	GSI	获取价格	ZBT SRAM
GS8161Z36DGT-333IV	GSI	获取价格	ZBT SRAM, 512KX36, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DGT-333T	GSI	获取价格	ZBT SRAM, 512KX36, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DGT-333V	GSI	获取价格	100 TQFP
GS8161Z36DGT-375	GSI	获取价格	ZBT SRAM, 512KX36, 4.2ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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