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GS8161Z36DT-150T PDF预览

GS8161Z36DT-150T

更新时间： 2024-11-19 14:42:23
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
38页 283K
描述
ZBT SRAM, 512KX36, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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GS8161Z36DT-150T 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.61
最长访问时间：7.5 ns其他特性：FLOW THROUGH OR PIPELINED ARCHITECTURE, ALSO OPERATES AT 3.3V
JESD-30 代码：R-PQFP-G100内存密度：18874368 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子位置：QUADBase Number Matches：1

GS8161Z36DT-150T 数据手册

 浏览型号GS8161Z36DT-150T的Datasheet PDF文件第2页浏览型号GS8161Z36DT-150T的Datasheet PDF文件第3页浏览型号GS8161Z36DT-150T的Datasheet PDF文件第4页浏览型号GS8161Z36DT-150T的Datasheet PDF文件第5页浏览型号GS8161Z36DT-150T的Datasheet PDF文件第6页浏览型号GS8161Z36DT-150T的Datasheet PDF文件第7页 
Preliminary  
GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D)  
400 MHz–150 MHz  
1.8 V, 2.5 V, or 3.3 V VDD  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V, 2.5 V, or 3.3 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable, ZZ and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• User-configurable Pipeline and Flow Through mode  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization  
• Fully pin-compatible with both pipelined and flow through  
NtRAM™, NoBL™ and ZBT™ SRAMs  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V, 2.5 V, or 3.3 V +10%/–10% core power supply  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and  
144Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ pin for automatic power-down  
• JEDEC-standard 165-bump BGA package  
• RoHS-compliant 100-pin TQFP and 165-bump BGA  
packages available  
The GS8161Z18D(GT/D)/GS8161Z32D(D)/  
GS8161Z36D(GT/D) may be configured by the user to operate  
in Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, in addition to the rising-edge-triggered  
registers that capture input signals, the device incorporates a  
rising-edge-triggered output register. For read cycles, pipelined  
SRAM output data is temporarily stored by the edge triggered  
output register during the access cycle and then released to the  
output drivers at the next rising edge of clock.  
Functional Description  
The GS8161Z18D(GT/D)/GS8161Z32D(D)/  
GS8161Z36D(GT/D) is an 18Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8161Z18D(GT/D)/GS8161Z32D(D)/  
GS8161Z36D(GT/D) is implemented with GSI's high  
performance CMOS technology and is available in JEDEC-  
standard 165-bump BGA package.  
Parameter Synopsis  
-400  
-375  
2.5  
2.66  
-333  
2.5  
3.3  
-250  
-200  
-150  
Unit  
t
2.5  
2.5  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
mA  
mA  
t
4.0  
4.0  
4.2  
4.2  
4.5  
4.5  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
mA  
mA  
Rev: 1.00 6/2011  
1/38  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...38

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 		ZBT SRAM, 512KX36, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-250VT GSI

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 		ZBT SRAM, 512KX36, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-333I GSI

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 		ZBT SRAM, 512KX36, 4.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-333IT GSI

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