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GS8161Z36DGT-250 PDF预览

GS8161Z36DGT-250

更新时间： 2024-11-24 13:47:59
品牌 Logo 应用领域
GSI /
页数 文件大小 规格书
40页 546K
描述
100 TQFP

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中文翻译

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GS8161Z36DGT-250 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：10 weeks风险等级：5.26
最长访问时间：5.5 ns其他特性：ALSO OPERATES AT 3.3V
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.6 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mm

GS8161Z36DGT-250 数据手册

 浏览型号GS8161Z36DGT-250的Datasheet PDF文件第2页浏览型号GS8161Z36DGT-250的Datasheet PDF文件第3页浏览型号GS8161Z36DGT-250的Datasheet PDF文件第4页浏览型号GS8161Z36DGT-250的Datasheet PDF文件第5页浏览型号GS8161Z36DGT-250的Datasheet PDF文件第6页浏览型号GS8161Z36DGT-250的Datasheet PDF文件第7页 
GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D)  
400 MHz–150 MHz  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V, 2.5 V, or 3.3 V V  
DD  
1.8 V, 2.5 V, or 3.3 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable, ZZ and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• User-configurable Pipeline and Flow Through mode  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization  
• Fully pin-compatible with both pipelined and flow through  
NtRAM™, NoBL™ and ZBT™ SRAMs  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V, 2.5 V, or 3.3 V +10%/–10% core power supply  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and  
144Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ pin for automatic power-down  
• JEDEC-standard 165-bump BGA package  
• RoHS-compliant 100-pin TQFP and 165-bump BGA  
packages available  
The GS8161Z18D(GT/D)/GS8161Z32D(D)/  
GS8161Z36D(GT/D) may be configured by the user to operate  
in Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, in addition to the rising-edge-triggered  
registers that capture input signals, the device incorporates a  
rising-edge-triggered output register. For read cycles, pipelined  
SRAM output data is temporarily stored by the edge triggered  
output register during the access cycle and then released to the  
output drivers at the next rising edge of clock.  
Functional Description  
The GS8161Z18D(GT/D)/GS8161Z32D(D)/  
GS8161Z36D(GT/D) is an 18Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8161Z18D(GT/D)/GS8161Z32D(D)/  
GS8161Z36D(GT/D) is implemented with GSI's high  
performance CMOS technology and is available in JEDEC-  
standard 165-bump BGA package.  
Parameter Synopsis  
-400  
-375  
-333  
-250  
-200  
-150  
Unit  
t
2.5  
2.5  
2.5  
2.66  
2.5  
3.3  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
370  
430  
350  
410  
310  
365  
250  
290  
210  
240  
185  
200  
mA  
mA  
t
4.0  
4.0  
4.2  
4.2  
4.5  
4.5  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
275  
315  
265  
300  
255  
285  
220  
250  
205  
225  
190  
205  
mA  
mA  
Rev: 1.03b 9/2013  
1/40  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...40

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