Datasheet > 存储 > SRAM> GS8161E18BGT-150V

GS8161E18BGT-150V

更新时间： 2024-11-30 05:10:43

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
35页	1504K
描述
1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs

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Preliminary

GS8161ExxB(T/D)-xxxV

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

250 MHz–150 MHz

1M x 18, 512K x 36, 512K x 36

18Mb Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V core power supply

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode pin (Pin 14). Holding the FT mode pin low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipeline mode, activating the rising-edge-triggered Data

Output Register.

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

DCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165 BGA packages

• RoHS-compliant 100-lead TQFP and 165 BGA packages

available

The GS8161ExxB(T/D)-xxxV is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of clock.

Functional Description

Byte Write and Global Write

Applications

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

The GS8161ExxB(T/D)-xxxV is a 18,874,368-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

Core and Interface Voltages

The GS8161ExxB(T/D)-xxxV operates on a 1.8 V or 2.5 V power

supply. All inputs are 1.8 V or 2.5 V compatible. Separate output

power (V_DDQ) pins are used to decouple output noise from the

internal circuits and are 1..8 V or 2.5 V compatible.

Parameter Synopsis

-250

-200

-150

Unit

t_KQ

tCycle

3.0

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

280

330

230

270

185

210

Curr (x18)

Curr (x32/x36)

t_KQ

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

210

240

185

205

170

190

Curr (x18)

Curr (x32/x36)

Rev: 1.01a 6/2006

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

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与GS8161E18BGT-150V相关器件

型号	品牌	获取价格	描述	数据表
GS8161E18BGT-150VT	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161E18BGT-200	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-200I	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-200IT	GSI	获取价格	暂无描述
GS8161E18BGT-200IV	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-200IVT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161E18BGT-200T	GSI	获取价格	暂无描述
GS8161E18BGT-200V	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-200VT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161E18BGT-250	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs

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