GS8161E18BGT-200T

更新时间： 2024-11-20 13:07:59

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器
页数	文件大小	规格书
35页	1504K
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GS8161E18BGT-200T 数据手册

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GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

250 MHz–150 MHz

1M x 18, 512K x 36, 512K x 36

18Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline operation

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP and 165-bump BGA packages

available

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)

is a DCD (Dual Cycle Deselect) pipelined synchronous

SRAM. SCD (Single Cycle Deselect) versions are also

available. DCD SRAMs pipeline disable commands to the

same degree as read commands. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock.

Functional Description

Applications

The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)

is a 18,874,368-bit high performance synchronous SRAM with

a 2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx,

BW, GW) are synchronous and are controlled by a positive-

edge-triggered clock input (CK). Output enable (G) and power

down control (ZZ) are asynchronous inputs. Burst cycles can

be initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)

operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V

and 2.5 V compatible. Separate output power (V

) pins are

DDQ

used to decouple output noise from the internal circuits and are

3.3 V and 2.5 V compatible.

Parameter Synopsis

-250

-200

-150

Unit

t_KQ

2.5

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

295

345

245

285

200

225

Curr (x18)

Curr (x32/x36)

t_KQ

tCycle

5.5

6.5

7.5

Flow Through

2-1-1-1

225

255

200

220

185

205

Curr (x18)

Curr (x32/x36)

Rev: 1.03 9/2005

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

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与GS8161E18BGT-200T相关器件

型号	品牌	获取价格	描述	数据表
GS8161E18BGT-200V	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-200VT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161E18BGT-250	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-250I	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-250IV	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-250IVT	GSI	获取价格	暂无描述
GS8161E18BGT-250T	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161E18BGT-250V	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-250VT	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161E18BT	GSI	获取价格	1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs

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