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GS8161E18BGD-250IVT PDF预览

GS8161E18BGD-250IVT

更新时间： 2024-11-20 20:52:31
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
34页 2224K
描述
Cache SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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GS8161E18BGD-250IVT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.64
最长访问时间：5.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 2.5V SUPPLY
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

GS8161E18BGD-250IVT 数据手册

 浏览型号GS8161E18BGD-250IVT的Datasheet PDF文件第2页浏览型号GS8161E18BGD-250IVT的Datasheet PDF文件第3页浏览型号GS8161E18BGD-250IVT的Datasheet PDF文件第4页浏览型号GS8161E18BGD-250IVT的Datasheet PDF文件第5页浏览型号GS8161E18BGD-250IVT的Datasheet PDF文件第6页浏览型号GS8161E18BGD-250IVT的Datasheet PDF文件第7页 
GS8161ExxB(T/D)-xxxV  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
250 MHz–150 MHz  
1M x 18, 512K x 36, 512K x 36  
18Mb Sync Burst SRAMs  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
ADV. The burst address counter may be configured to count in  
either linear or interleave order with the Linear Burst Order (LBO)  
input. The Burst function need not be used. New addresses can be  
loaded on every cycle with no degraation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V or 2.5 V core power supply  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by the  
user via the FT mode pin (Pin 14). Holding the FT mode pin low  
places the RAM in Flow Through mode, causing output data to  
bypass the Data Output Register. Holding FT high places the  
RAM in Pipeline mode, activating the rising-edge-triggered Data  
Output Register.  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
DCD Pipelined Reads  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP and 165 BGA packages  
• RoHS-compliant 100-lead TQFP and 165 BGA packages  
available  
The GS8161ExxB(T/D)-xxxV is a DCD (Dual Cycle Deselect)  
pipelined synchronous SRAM. SCD (Single Cycle Deselect)  
versions e also available. DCD SRAMs pipeline disable  
commands to the same degree as read commands. DCD RAMs  
hold the deselect command for one full cycle and then begin  
turning off their outputs just after the second rising edge of clock.  
Functional Description  
Byte Write and Global Write  
Applications  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write control  
inputs.  
The GS8161ExxB(T/D)-xxxV is a 18,874,368-bit high  
performance synchronous SRAM with a 2-bit burst address  
counter. Although of a type originally developed for Level 2  
Cache applications supporting high performance CPUs, the device  
now finds application in synchronous SRAM applications, ranging  
from DSP main store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High)  
of the ZZ signal, or by stopping the clock (CK). Memory data is  
retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,  
GW) are synchronous and are controlled by a positive-edge-  
triggered clock input (CK). Output enable (G) and power down  
control (ZZ) are asynchronous inputs. Burst cycles can be initiated  
with either ADSP or ADSC inputs. In Burt mode, subsequent  
burst addresses are generated internally and are controlled by  
Core and Interface Voltages  
The GS8161ExxB(T/D)-xxxV operates on a 1.8 V or 2.5 V power  
supply. All inputs are 1.8 V or 2.5 V compatible. Separate output  
power (VDDQ) pins are used to decouple output noise from the  
internal circuits and are 1..8 V or 2.5 V compatible.  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
tCycle  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
Pipeline  
3-1-1-1  
280  
330  
230  
270  
185  
210  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
210  
240  
185  
205  
170  
190  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.03 9/2008  
1/34  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...34

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