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GS8160F36GT-7.5T PDF预览

GS8160F36GT-7.5T

更新时间： 2024-11-08 07:39:35
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
22页 564K
描述
Cache SRAM, 512KX36, 7.5ns, CMOS, PQFP100, TQFP-100

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GS8160F36GT-7.5T 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.71最长访问时间：7.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：PURE MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

GS8160F36GT-7.5T 数据手册

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GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5  
5.5 ns–8.5 ns  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
1M x 18, 512K x 32, 512K x 36  
18Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• Flow Through mode operation; Pin 14 = No Connect  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
Designing For Compatibility  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
The JEDEC standard for Burst RAMS calls for a FT mode pin  
option on Pin 14. Board sites for flow through Burst RAMS  
should be designed with V connected to the FT pin location  
SS  
to ensure the broadest access to multiple vendor sources.  
Boards designed with FT pin pads tied low may be stuffed with  
GSI’s pipeline/flow through-configurable Burst RAMs or any  
vendor’s flow through or configurable Burst SRAM. Boards  
designed with the FT pin location tied high or floating must  
employ a non-configurable flow through Burst RAM, like this  
RAM, to achieve flow through functionality.  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
Functional Description  
Applications  
The GS8160F18/32/36T is an 18,874,368-bit (16,777,216-bit  
for x32 version) high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Sleep Mode  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS8160F18/32/36T operates on a 2.5 V or 3.3 V power  
supply. All input are 3.3 V and 2.5 V compatible. Separate  
output power (V  
) pins are used to decouple output noise  
DDQ  
from the internal circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-5.5 -6 -6.5 -7 -7.5 -8.5 Unit  
Flow  
Through  
2-1-1-1  
tKQ  
5.5  
5.5  
6.0  
6.0  
6.5  
6.5  
7.0  
7.0  
7.5  
7.5  
8.5  
8.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x32/x36) 200  
175  
165  
190  
160  
180  
150  
170  
145 135  
165 150  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18) 175  
Curr (x32/x36) 200  
165  
190  
160  
180  
150  
170  
145 135  
165 150  
mA  
mA  
Rev: 2.12 11/2004  
1/22  
© 1999, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...22

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