Datasheet > GS8152Z18B-200T

GS8152Z18B-200T

更新时间： 2024-11-08 06:00:11

品牌	Logo	应用领域
GSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
39页	757K
描述
ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119

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技术参数
数据手册

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GS8152Z18B-200T 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	BGA, BGA119,7X17,50	Reach Compliance Code：	compliant
风险等级：	5.88	最长访问时间：	7.5 ns
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
内存密度：	18874368 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	湿度敏感等级：	3
端子数量：	119	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
最大待机电流：	0.01 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.281 mA
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	Base Number Matches：	1

GS8152Z18B-200T 数据手册

Preliminary

GS8152Z18/36/72B-225/200/180/166/150/133

119 and 209 BGA

_{Commercial Temp}16Mb Pipelined and Flow Through ^{225MHz–133MHz}

3.3 V V

Industrial Temp

Synchronous NBT SRAM

2.5 V or 3.3 V I/O

Features

Functional Description

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

The GS8152Z18/36/72B is a 16Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119- or 209-Bump BGA package

-225 -200 -180 -166 -150 -133 Unit

The GS8152Z18/36/72B may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

Flow

t_KQ

7.0 7.5 8.0 8.5 10.0 11.0 ns

8.5 10.0 10.0 10.0 10.0 15.0 ns

205 185 185 185 185 140 mA

240 210 210 210 210 160 mA

325 285 285 285 285 205 mA

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

Pipeline

3-1-1-1

t_KQ

tCycle

2.5 3.0 3.2 3.5 3.8 4.0 ns

4.4 5.0 5.5 6.0 6.7 7.5 ns

350 315 290 270 250 230 mA

410 370 340 315 290 260 mA

570 515 470 435 400 360 mA

Curr (x18)

Curr (x36)

Curr (x72)

The GS8152Z18/36/72B is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 119-bump (x18 & x36) or 209-bump (x72) BGA

package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Q_A

D_B

Q_C

D_D

Q_E

Pipelined

Data I/O

Q_A

D_B

Q_C

D_D

Q_E

Rev: 1.01 11/2000

1/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

12 3 4 5 6 7...39

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与GS8152Z18B-200T相关器件

型号	品牌	获取价格	描述	数据表
GS8152Z18B-225T	GSI	获取价格	ZBT SRAM, 1MX18, 7ns, CMOS, PBGA119
GS8152Z36B-180T	GSI	获取价格	ZBT SRAM, 512KX36, 8ns, CMOS, PBGA119
GS8152Z36B-200	GSI	获取价格	ZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA119
GS8152Z36B-200T	GSI	获取价格	ZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA119
GS8152Z72B-133I	GSI	获取价格	ZBT SRAM, 256KX72, 11ns, CMOS, PBGA209
GS8152Z72B-133IT	GSI	获取价格	ZBT SRAM, 256KX72, 11ns, CMOS, PBGA209
GS8152Z72B-150I	GSI	获取价格	ZBT SRAM, 256KX72, 10ns, CMOS, PBGA209
GS8152Z72B-150IT	GSI	获取价格	ZBT SRAM, 256KX72, 10ns, CMOS, PBGA209
GS8152Z72B-225T	GSI	获取价格	ZBT SRAM, 256KX72, 7ns, CMOS, PBGA209
GS8-16	ETC	获取价格	RING TONGUE TERMINAL Non-insulated DIN 46234

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