Datasheet > GS816018AT-225T

GS816018AT-225T

更新时间： 2024-11-09 15:42:11

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
26页	748K
描述
Cache SRAM, 1MX18, 6ns, CMOS, PQFP100, TQFP-100

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技术参数
数据手册

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GS816018AT-225T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.72
最长访问时间：	6 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	18874368 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.6 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS816018AT-225T 数据手册

Preliminary

GS816018/32/36AT-300/275/250/225/200

300 MHz–200 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

1M x 18, 512K x 32, 512K x 36

1.8 V or 2.5 V V_DD

1.8 V or 2.5 V I/O

18Mb Sync Burst SRAMs

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode pin

low places the RAM in Flow Through mode, causing output

data to bypass the Data Output Register. Holding FT high

places the RAM in Pipeline mode, activating the rising-edge-

triggered Data Output Register.

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

-300 -275 -250 -225 -200 Unit

Byte Write and Global Write

Pipeline

3-1-1-1

2.2 2.4 2.5 2.7 3.0 ns

3.3 3.6 4.0 4.4 5.0 ns

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

tCycle

Curr (x18)

320 300 275 250 230 mA

2.5 V

1.8 V

Curr (x32/x36) 375 345 320 295 265 mA

Curr (x18) 320 300 275 250 225 mA

Curr (x32/x36) 370 340 315 285 260 mA

Sleep Mode

Flow

Through

2-1-1-1

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

5.0 5.25 5.5 6.0 6.5 ns

tCycle

Curr (x18)

220 215 210 200 190 mA

Core and Interface Voltages

2.5 V

1.8 V

Curr (x32/x36) 265 260 245 235 225 mA

Curr (x18) 220 215 210 200 190 mA

Curr (x32/x36) 265 260 245 235 225 mA

The GS816018/32/36AT operates on a 1.8 V or 2.5 V power

supply. All inputs are 2.5 V and 1.8 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 2.5 V and 1.8 V compatible.

Functional Description

Applications

The GS816018/32/36AT is a 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Rev: 1.02a 9/2002

1/26

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...26

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与GS816018AT-225T相关器件

型号	品牌	获取价格	描述	数据表
GS816018AT-250I	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, TQFP-100
GS816018AT-250IT	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, TQFP-100
GS816018AT-250T	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, TQFP-100
GS816018AT-275IT	GSI	获取价格	Cache SRAM, 1MX18, 5.25ns, CMOS, PQFP100, TQFP-100
GS816018AT-300	GSI	获取价格	Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, TQFP-100
GS816018AT-300IT	GSI	获取价格	Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, TQFP-100
GS816018BGT-150	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BGT-150I	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BGT-150IT	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS816018BGT-150IV	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

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