Datasheet > GS816018AGT-150

GS816018AGT-150

更新时间： 2024-11-08 06:11:31

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
23页	481K
描述
Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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数据手册

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GS816018AGT-150 数据手册

Preliminary

GS816018/32/36AT-300/250/200/150

300 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

1M x 18, 512K x 32, 512K x 36

2.5 V or 3.3 V V_DD

2.5 V or 3.3 V I/O

18Mb Sync Burst SRAMs

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode pin

low places the RAM in Flow Through mode, causing output

data to bypass the Data Output Register. Holding FT high

places the RAM in Pipeline mode, activating the rising-edge-

triggered Data Output Register.

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Byte Write and Global Write

Functional Description

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS816018/32/36AT is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Core and Interface Voltages

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

The GS816018/32/36AT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-300

-250

-200

-150

Unit

t_KQ(x18/x36)

tCycle

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

335

390

280

330

230

270

185

210

Curr (x18)

Curr (x32/x36)

t_KQ

tCycle

5.0

5.5

6.5

7.5

Flow Through

2-1-1-1

230

270

210

240

185

205

170

190

Curr (x18)

Curr (x32/x36)

Rev: 1.03a 5/2003

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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与GS816018AGT-150相关器件

型号	品牌	获取价格	描述	数据表
GS816018AGT-150I	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-150IT	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-150T	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-200I	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-200IT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-225IT	GSI	获取价格	Cache SRAM, 1MX18, 6ns, CMOS, PQFP100, TQFP-100
GS816018AGT-250I	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-275IT	GSI	获取价格	Cache SRAM, 1MX18, 5.25ns, CMOS, PQFP100, TQFP-100
GS816018AGT-300	GSI	获取价格	Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, TQFP-100
GS816018AGT-300I	GSI	获取价格	Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, TQFP-100

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