Datasheet > GS81302D06E-500I

GS81302D06E-500I

更新时间： 2024-12-01 01:24:15

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
31页	526K
描述
JEDEC-standard pinout and package

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数据手册

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GS81302D06E-500I 数据手册

GS81302D06/11/20/38E-500/450/400/350

500 MHz–350 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

144Mb SigmaQuad-II+

Burst of 4 SRAM

1.8 V V

1.8 V or 1.5 V I/O

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) intputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Clocking and Addressing Schemes

The GS81302D06/11/20/38E SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 16M x 8 has a

4M addressable index).

SigmaQuad™ Family Overview

The GS81302D06/11/20/38E are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302D06/11/20/38E SigmaQuad SRAMs

Parameter Synopsis

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-350

tKHKH

tKHQV

2.86 ns

0.45 ns

Rev: 1.05c 8/2017

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...31

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与GS81302D06E-500I相关器件

型号	品牌	获取价格	描述	数据表
GS81302D06GE-350	GSI	获取价格	JEDEC-standard pinout and package
GS81302D06GE-350I	GSI	获取价格	144Mb SigmaQuad-II Burst of 4 SRAM
GS81302D06GE-400	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, FPBGA-165
GS81302D06GE-400I	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, FPBGA-165
GS81302D06GE-400IT	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS81302D06GE-400T	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS81302D06GE-450	GSI	获取价格	DDR SRAM, 16MX8, 0.37ns, CMOS, PBGA165, FPBGA-165
GS81302D06GE-450I	GSI	获取价格	Dual Double Data Rate interface
GS81302D06GE-450IT	GSI	获取价格	DDR SRAM, 16MX8, 0.37ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS81302D06GE-500	GSI	获取价格	165 BGA

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