GS71116ATP/J/U
6, 8, 10, 12 ns
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
64K x 16
3.3 V V
DD
Center V and V
DD
SS
1Mb Asynchronous SRAM
SOJ 64K x 16-Pin Configuration
Features
• Fast access time: 6, 8, 10, 12 ns
• CMOS low power operation: 165/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
A4
1
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
A6
2
A2
A7
3
A1
OE
4
Top view
A0
UB
5
CE
LB
6
DQ1
DQ2
DQ3
DQ4
DQ16
DQ15
DQ14
7
8
9
10
11
12
13
14
15
DQ13
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
44-pin
SOJ
V
DD
V
V
SS
V
SS
DD
DQ5
DQ6
DQ7
DQ8
WE
DQ12
DQ11
DQ10
DQ9
NC
Description
16
17
18
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 400 mil SOJ and 400
mil TSOP Type-II packages.
A15
A14
A13
A12
NC
A8
A9
19
20
21
22
A10
A11
NC
Package J
Pin Descriptions
Fine Pitch BGA 64K x 16-Bump Configuration
Symbol
A0–A15
Description
Address input
1
2
3
4
5
6
DQ1–DQ16
Data input/output
Chip enable input
CE
A
B
C
LB
OE
A0
A3
A1
A4
A6
A2
NC
Lower byte enable input
(DQ1 to DQ8)
LB
DQ16 UB
CE
DQ1
Upper byte enable input
(DQ9 to DQ16)
DQ14 DQ15 A5
DQ2 DQ3
UB
VSS
VDD
VDD
VSS
D
E
DQ13 NC
DQ12 NC
A7
DQ4
WE
OE
Write enable input
Output enable input
+3.3 V power supply
NC DQ5
VDD
F
G
H
DQ11 DQ10 A8
A9
DQ7 DQ6
WE DQ8
VSS
NC
Ground
DQ9 NC
NC A12
A10
A13
A11
A14
No connect
A15
NC
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)
© 2001, Giga Semiconductor, Inc.
Rev: 1.03 3/2002
1/15
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.