G M 71V 65803C
G M 71V S65803CL
8,388,608 WORDS x 8 BIT
CMOS DYNAMIC RAM
D escription
Pin Configuration
32 SOJ / TSOP II
T h e GM 71V ( S)65803C/ C L i s t h e n e w
generation dynamic RA M organized 8,388,608
w o r d s by 8bits. T h e GM 71V (S)65803C/ CL
utilizes advanced CM O S Silicon Gate Process
Technology as w ell as advanced circuit
techniques for w ide operating margins, both
i n t er n al l y and to the system u ser . Sy st em
oriented features include single pow er supply of
3.3V + / -10% tolerance, d i r ect i n t erfacing
capability w ith high performance logic families
such as Schottky TTL.
1
2
3
32
31
VSS
IO7
VCC
IO0
IO1
IO2
IO3
NC
30
IO6
4
5
6
7
29
28
27
26
IO5
IO4
VSS
VCC
/CAS
The GM 71V (S)65803C/ CL offers Extended
Data Out (EDO) M ode as a high speed access
mode.
8
9
25
/OE
/WE
/RAS
24 NC
10
A0
23 A11
22 A10
Features
* 8,388,608 Words x 8 Bit
* Extended Data Out (EDO) M ode Capability
* Fast A ccess Tim e & Cycle Tim e
11
12
A1
A2
A3
A9
21
A8
A7
20
19
13
14
15
(Unit: ns)
A4
A5
t
RAC
50
t
A A
t
CAC
13
t
RC
t
H PC
18 A6
VSS
84
20
25
25
30
G M 71V (S)65803C/ CL-5
G M 71V (S)65803C/ CL-6
16
17
VCC
15
104
60
(Top View)
*Pow er dissipation
- A ctive : 522m W / 486mW(M A X)
- Standby : 1.8 mW ( CM OS level : M A X )
0.54mW ( L-Version : M A X)
*EDO page mode capability
*A ccess tim e : 50ns/ 60ns (m ax)
*Refresh cycles
- RA S only Refresh
4096 cycles/ 64 m s (GM 71V65803C)
4096 cycles/ 128m s (GM 71V S65803CL)(L_Version)
*CBR & H idden Refresh
4096 cycles/ 64 m s (GM 71V65803C)
4096 cycles/ 128 m s (GM 71VS65803CL)( L-Version )
*4 variations of refresh
-RA S-only refresh
-CA S-before-RA S refresh
-H idden refresh
-Self refresh (L-V ersion)
*Single Pow er Supply of 3.3V+/ -10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
Rev 0.1 / Apr’01