Datasheet > FW801A-DB

FW801A-DB

更新时间： 2024-01-19 19:21:46

品牌	Logo	应用领域
杰尔 - AGERE		驱动器接口集成电路
页数	文件大小	规格书
24页	363K
描述
Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device

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FW801A-DB 技术参数

生命周期：	Active	包装说明：	LFQFP, QFP48,.35SQ,20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.6
差分输出：	YES	驱动器位数：	2
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	IEEE 1394	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e0	长度：	7 mm
功能数量：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：
最小输出摆幅：	0.172 V	最大输出低电流：	0.012 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP48,.35SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	240
电源：	3.3 V	认证状态：	Not Qualified
接收器位数：	2	座面最大高度：	1.6 mm
子类别：	Line Driver or Receivers	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	7 mm	Base Number Matches：	1

FW801A-DB 数据手册

Data Sheet, Rev. 1

June 2001

FW801A Low-Power PHY IEEE 1394A-2000

One-Cable Transceiver/Arbiter Device

^ISupports connection debounce.

^ISupports multispeed packet concatenation.

Distinguishing Features

^ICompliant with IEEE Standard 1394a-2000,

IEEE Standard for a High Performance Serial

Bus Amendment 1.

^ISupports PHY pinging and remote PHY access

packets.

^IFully supports suspend/resume.

^ISupports PHY-link interface initialization and reset.

^ISupports 1394a-2000 register set.

^ILow power consumption during powerdown or

microlow-power sleep mode.

^ISupports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders.

^IWhile unpowered and connected to the bus, will

not drive TPBIAS on the connected port even if

receiving incoming bias voltage on the port.

^IDoes not require external filter capacitors for PLL.

^IDoes not require a separate 5 V supply for 5 V link

controller interoperability.

^IInteroperable across 1394 cable with 1394 physi-

cal layers (PHY) using 5 V supplies.

^IInteroperable with 1394 link-layer controllers using

5 V supplies.

^ISupports LPS/link-on as a part of PHY-link inter-

face.

^ISupports provisions of IEEE 1394-1995 Standard

for a High Performance Serial Bus.

^IFully interoperable with FireWire^†implementation

of IEEE 1394-1995.

^IReports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V.

^ISeparate cable bias and driver termination voltage

supply for the port.

^IMeets Intel^‡Mobile Power Guideline 2000.

^I1394a-2000 compliant common mode noise filter

on incoming TPBIAS.

Other Features

^I48-pin TQFP package.

^IPowerdown features to conserve energy in bat-

tery-powered applications include:

— Device powerdown pin.

^ISingle 3.3 V supply operation.

— Link interface disable using LPS.

— Inactive ports power down.

^IData interface to link-layer controller provided

through 2/4/8 parallel lines at 50 Mbits/s.

— Automatic microlow-power sleep mode during

^I25 MHz crystal oscillator and PLL provide transmit/

receive data at 100 Mbits/s, 200 Mbits/s, and

400 Mbits/s, and link-layer controller clock at

50 MHz.

suspend.

^IInterface to link-layer controller supports Annex J

electrical isolation as well as bus-keeper isolation.

^INode power-class information signaling for system

power management.

Features

^IMultiple separate package signals provided for

analog and digital supplies and grounds.

^IProvides one fully compliant cable port at

100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

^IFully supports OHCI requirements.

^ISupports arbitrated short bus reset to improve

utilization of the bus.

^ISupports ack-accelerated arbitration and fly-by

concatenation.

* IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

†FireWire is a registered trademark of Apple Computer, Inc.

‡Intel is a registered trademark of Intel Corporation.

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