Datasheet > FW803-09-DB

FW803-09-DB

更新时间： 2024-01-26 21:43:38

品牌	Logo	应用领域
杰尔 - AGERE		驱动器接口集成电路
页数	文件大小	规格书
24页	378K
描述
PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device

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FW803-09-DB 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LFQFP, QFP64,.47SQ,20	针数：	64
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.65
差分输出：	YES	驱动器位数：	6
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	IEEE 1394	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	10 mm
功能数量：	1	端子数量：	64
最高工作温度：	70 °C	最低工作温度：
最小输出摆幅：	0.172 V	最大输出低电流：	0.012 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP64,.47SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	240
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：		接收器位数：	6
座面最大高度：	1.6 mm	子类别：	Line Driver or Receivers
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	10 mm
Base Number Matches：	1

FW803-09-DB 数据手册

Data Sheet, Rev. 3

June 2001

FW803 PHY IEEE*1394A

Three-Cable Transceiver/Arbiter Device

^ISupports LPS/link-on as a part of PHY-link interface.

Distinguishing Features

^ISupports provisions of IEEE 1394-1995 Standard for

a High Performance Serial Bus.

^ICompliant with IEEE P1394a Draft 2.0 Standard

for a High Performance Serial Bus (Supplement)

^ISupports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders.

^IWhile unpowered and connected to the bus, will not

drive TPBIAS on a connected port even if receiving

incoming bias voltage on that port.

†

^IFully interoperable with FireWire implementation of

IEEE 1394-1995.

^IReports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V.

^ISeparate cable bias and driver termination voltage

supply for each port.

^IDoes not require external filter capacitors for PLL.

^IDoes not require a separate 5 V supply for 5 V link

controller interoperability.

Other Features

^IInteroperable across 1394 cable with 1394 physical

layers (PHY) using 5 V supplies.

^IInteroperable with 1394 link-layer controllers using

5 V supplies.

^I64-pin TQFP package.

^ISingle 3.3 V supply operation.

^IData interface to link-layer controller provided

through 2/4/8 parallel lines at 50 Mbits/s.

^I25 MHz crystal oscillator and PLL provide transmit/

receive data at 100 Mbits/s, 200 Mbits/s, and

400 Mbits/s, and link-layer controller clock at

50 MHz.

^INode power-class information signaling for system

power management.

^IMultiple separate package signals provided for ana-

log and digital supplies and grounds.

^IPowerdown features to conserve energy in battery-

powered applications include:

— Device powerdown pin.

— Link interface disable using LPS.

— Inactive ports power down.

^IInterface to link-layer controller supports Annex J

electrical isolation as well as bus-keeper isolation.

Features

^IProvides three fully compliant cable ports at

100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

^IFully supports open HCI requirements.

^ISupports arbitrated short bus reset to improve

utilization of the bus.

Description

The Agere Systems Inc. FW803 device provides the

analog physical layer functions needed to implement a

three-port node in a cable-based IEEE 1394-1995 and

IEEE 1394a-2000 network.

^ISupports ack-accelerated arbitration and fly-by con-

catenation.

^ISupports connection debounce.

^ISupports multispeed packet concatenation.

^ISupports PHY pinging and remote PHY access

packets.

^IFully supports suspend/resume.

* IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

†FireWire is a registered trademark of Apple Computer, Inc.

^ISupports PHY-link interface initialization and reset.

^ISupports 1394a-2000 register set.

12 3 4 5 6 7...24

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