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FW80321M400Q466B-1 PDF预览

FW80321M400Q466B-1

更新时间: 2024-01-18 11:32:37
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
54页 392K
描述
Micro Peripheral IC, PBGA544

FW80321M400Q466B-1 技术参数

生命周期:Active包装说明:BGA, BGA544,26X26,50
Reach Compliance Code:compliant风险等级:5.65
JESD-30 代码:S-PBGA-B544端子数量:544
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA544,26X26,50封装形状:SQUARE
封装形式:GRID ARRAY电源:1.3,2.5,3.3 V
认证状态:Not Qualified子类别:Other Microprocessor ICs
表面贴装:YES端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
Base Number Matches:1

FW80321M400Q466B-1 数据手册

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Intel® 80321 I/O Processor  
Datasheet  
Product Features  
Core Features  
DMA Controller  
Integrated Intel® XScaleCore  
ARM* V5T Instruction Set  
ARM V5E DSP Extensions  
400 MHz and 600 MHz  
Write Buffer, Write-back Cache  
PCI Bus Interface  
Two Independent Channels Connected  
to Internal Bus  
Up to 1064 Mbytes/s Burst Support in  
PCI-X Mode  
Up to 1600 Mbytes/s Burst Support for  
Internal Bus  
Two 1-Kbyte Queues in Ch-0 and Ch-1  
232 Addressing Range on Internal Bus  
Interface  
PCI Local Bus Specification, Rev. 2.2  
compliant  
264 Addressing Range on PCI Interface  
Application Accelerator Unit  
PCI-X Addendum to the PCI Local Bus  
Specification, Rev. 1.0a  
64-bit/66 MHz Operation in PCI Mode  
Performs XOR on Read Data  
64-bit/133 MHz Operation in PCI-X  
Mode  
Compute Parity Across Local Memory  
Blocks  
Support 32-bit PCI Initiators and Targets  
Four Split Read Requests as Initiator  
Eight Split Read Requests as Target  
64-bit Addressing Support  
—1 Kbyte/512-byte Store Queue  
I2C Bus Interface Units  
Two Separate I2C Units  
Serial Bus  
Master/Slave Capabilities  
Memory Controller  
System Management Functions  
SSP Serial Port  
PC200 Double Data Rate (DDR) SDRAM  
Up to 1 Gbyte of 64-bit DDR SDRAM  
Full-duplex Synchronous Serial Interface  
Supports 7.2 KHz to 1.84 MHz Bit Rates  
Peripheral Performance Monitoring Unit  
One Dedicated Global Time Stamp  
Counter  
Fourteen Programmable Event Counters  
Three Control/Status Registers  
Timers  
Up to 512 Mbytes of 32-bit DDR  
SDRAM  
Single-bit Error Correction, Multi-bit  
Support (ECC)  
1024-byte Posted Memory Write Queue  
40- and 72-bit wide Memory Interface  
Address Translation Unit  
—2 Kbyte or 4 Kbyte Outbound Read  
Queue  
Two Dual-programmable 32-bit Timers  
Watchdog Timer  
—4 Kbyte Outbound Write Queue  
544-Ball, Plastic Ball Grid Array (PBGA)  
Eight General Purpose I/O Pins  
—4 Kbyte Inbound Read and Write Queue  
Connects Internal Bus to PCI/PCI-X Bus  
Document Number: 273518-005  
January 2005  

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