Datasheet > FW804-09-DB

FW804-09-DB

更新时间： 2024-09-28 22:25:51

品牌	Logo	应用领域
杰尔 - AGERE		驱动器接口集成电路
页数	文件大小	规格书
24页	382K
描述
PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device

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FW804-09-DB 数据手册

Data Sheet, Rev. 3

June 2001

FW804 PHY IEEE*1394A

Four-Cable Transceiver/Arbiter Device

^ISupports LPS/link-on as a part of PHY-link inter-

face.

Distinguishing Features

^ICompliant with IEEE P1394a Draft 2.0 Standard

for a High Performance Serial Bus (Supple-

ment)

^ISupports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders.

^IWhile unpowered and connected to the bus, will not

drive TPBIAS on a connected port even if receiving

incoming bias voltage on that port.

^ISupports provisions of IEEE 1394-1995 Standard

for a High Performance Serial Bus.

†

^IFully interoperable with FireWire implementation

of IEEE 1394-1995.

^IReports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V.

^ISeparate cable bias and driver termination voltage

supply for each port.

^IDoes not require external filter capacitors for PLL.

^IDoes not require a separate 5 V supply for 5 V link

controller interoperability.

Other Features

^IInteroperable across 1394 cable with 1394 physical

layers (PHY) using 5 V supplies.

^IInteroperable with 1394 link-layer controllers using

5 V supplies.

^I80-pin TQFP package.

^ISingle 3.3 V supply operation.

^IData interface to link-layer controller provided

through 2/4/8 parallel lines at 50 Mbits/s.

^I25 MHz crystal oscillator and PLL provide transmit/

receive data at 100 Mbits/s, 200 Mbits/s, and

400 Mbits/s, and link-layer controller clock at

50 MHz.

^IPowerdown features to conserve energy in battery-

powered applications include:

— Device powerdown pin.

— Link interface disable using LPS.

— Inactive ports power down.

^INode power-class information signaling for system

power management.

^IInterface to link-layer controller supports Annex J

electrical isolation as well as bus-keeper isolation.

^IMultiple separate package signals provided for

analog and digital supplies and grounds.

Features

^IProvides four fully compliant cable ports at

100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

^IFully supports open HCI requirements.

^ISupports arbitrated short bus reset to improve

utilization of the bus.

^ISupports ack-accelerated arbitration and fly-by

concatenation.

Description

The Agere Systems Inc. FW804 device provides the

analog physical layer functions needed to implement

a four-port node in a cable-based IEEE 1394-1995

and IEEE 1394a-2000 network.

^ISupports connection debounce.

^ISupports multispeed packet concatenation.

^ISupports PHY pinging and remote PHY access

packets.

* IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

†FireWire is a registered trademark of Apple Computer, Inc.

^IFully supports suspend/resume.

^ISupports PHY-link interface initialization and reset.

^ISupports 1394a-2000 register set.

12 3 4 5 6 7...24

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