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FW82371AB

更新时间： 2024-02-23 13:55:06
品牌 Logo 应用领域
英特尔 - INTEL PC
页数 文件大小 规格书
284页 1020K
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FW82371AB 数据手册

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E
82371AB PCI-TO-ISA / IDE  
XCELERATOR (PIIX4)  
Supported Kits for both Pentium® and  
Pentium® II Microprocessors  
¾ 82430TX ISA Kit  
¾ Integrated 16 x 32-bit Buffer for IDE  
PCI Burst Transfers  
¾ Supports Glue-less “Swap-Bay”  
Option with Full Electrical Isolation  
¾ 82440LX ISA/DP Kit  
Enhanced DMA Controller  
¾ Two 82C37 DMA Controllers  
¾ Supports PCI DMA with 3 PC/PCI  
Channels and Distributed DMA  
Protocols (Simultaneously)  
¾ Fast Type-F DMA for Reduced PCI  
Bus Usage  
Multifunction PCI to ISA Bridge  
¾ Supports PCI at 30 MHz and 33 MHz  
¾ Supports PCI Rev 2.1 Specification  
¾ Supports Full ISA or Extended I/O  
(EIO) Bus  
¾ Supports Full Positive Decode or  
Subtractive Decode of PCI  
¾ Supports ISA and EIO at 1/4 of PCI  
Frequency  
Interrupt Controller Based on Two  
82C59  
¾ 15 Interrupt Support  
¾ Independently Programmable for  
Edge/Level Sensitivity  
¾ Supports Optional I/O APIC  
¾ Serial Interrupt Input  
Supports both Mobile and Desktop  
Deep Green Environments  
¾ 3.3V Operation with 5V Tolerant  
Buffers  
¾ Ultra-low Power for Mobile  
Environments Support  
Timers Based on 82C54  
¾ Power-On Suspend, Suspend to  
RAM, Suspend to Disk, and Soft-  
OFF System States  
¾ All Registers Readable and  
Restorable for Proper Resume  
from 0.V Suspend  
¾ System Timer, Refresh Request,  
Speaker Tone Output  
USB  
¾ Two USB 1.0 Ports for Serial  
Transfers at 12 or 1.5 Mbit/sec  
¾ Supports Legacy Keyboard and  
Mouse Software with USB-based  
Keyboard and Mouse  
Power Management Logic  
¾ Global and Local Device  
Management  
¾ Supports UHCI Design Guide  
¾ Suspend and Resume Logic  
¾ Supports Thermal Alarm  
¾ Support for External  
Microcontroller  
¾ Full Support for Advanced  
Configuration and Power Interface  
(ACPI) Revision 1.0 Specification  
and OS Directed Power  
Management  
SMBus  
¾ Host Interface Allows CPU to  
Communicate Via SMBus  
¾ Slave Interface Allows External  
SMBus Master to Control Resume  
Events  
Real-Time Clock  
¾ 256-byte Battery-Back CMOS SRAM  
¾ Includes Date Alarm  
Integrated IDE Controller  
¾ Independent Timing of up to  
4 Drives  
¾ PIO Mode 4 and Bus Master IDE  
Transfers up to 14 Mbytes/sec  
¾ Supports “Ultra DMA/33”  
Synchronous DMA Mode Transfers  
up to 33 Mbytes/sec  
¾ Two 8-byte Lockout Ranges  
Microsoft Win95* Compliant  
324 mBGA Package  
© INTEL CORPORATION 1997  
April 1997  
Order Number: 290562-001  
4/9/97 2:23 PM PIIX4aDS  
INTEL CONFIDENTIAL  
(until publication date)  
1234567...284

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