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FW801BF

更新时间： 2024-01-26 22:18:58
品牌 Logo 应用领域
杰尔 - AGERE /
页数 文件大小 规格书
26页 529K
描述
Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device

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中文翻译

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FW801BF 技术参数

生命周期：Active包装说明：LFQFP, QFP48,.35SQ,20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.6
差分输出：YES驱动器位数：2
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：IEEE 1394JESD-30 代码：S-PQFP-G48
JESD-609代码：e0长度：7 mm
功能数量：1端子数量：48
最高工作温度：70 °C最低工作温度：
最小输出摆幅：0.172 V最大输出低电流：0.012 A
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
接收器位数：2座面最大高度：1.6 mm
子类别：Line Driver or Receivers最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

FW801BF 数据手册

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Data Sheet  
January 2005  
™
™
FW801BF Low-Power PHY 1394a-2000  
One-Cable Transceiver/Arbiter Device  
„ Supports PHY pinging and remote PHY access  
packets.  
Distinguishing Features  
®
„ Compliant with IEEE Standard 1394a-2000,  
„ Fully supports suspend/resume.  
IEEE Standard for a High Performance Serial  
Bus Amendment 1.  
„ Supports PHY-link interface initialization and reset.  
„ Supports 1394a-2000 register set.  
„ Low power consumption during powerdown or  
microlow-power sleep mode.  
„ Supports LPS/link-on as a part of PHY-link inter-  
face.  
„ Supports extended BIAS_HANDSHAKE time for  
enhanced interoperability with camcorders.  
„ Supports provisions of IEEE 1394-1995 Standard  
for a High Performance Serial Bus.  
„ While unpowered and connected to the bus, will  
not drive TPBIAS on a connected port even if  
receiving incoming bias voltage on that port.  
®
„ Fully interoperable with FireWire® and i.LINK  
implementations of IEEE 1394-1995.  
„ Reports cable power fail interrupt when voltage at  
CPS ball falls below 7.5 V.  
„ Does not require external filter capacitors for PLL.  
„ Does not require a separate 5 V supply for 5 V link  
controller interoperability.  
„ Provides separate cable bias and driver termination  
voltage supply for port.  
„ Interoperable across 1394 cable with 1394 physi-  
cal layers (PHY) using 5 V supplies.  
Other Features  
„ Interoperable with 1394 link-layer controllers using  
5 V supplies.  
„ 48-ball VTFSBGAC package.  
„ Single 3.3 V supply operation.  
„ 1394a-2000 compliant common mode noise filter  
on incoming TPBIAS.  
„ Powerdown features to conserve energy in bat-  
tery-powered applications include the following:  
— Device powerdown ball.  
— Link interface disable using LPS.  
— Inactive ports power down.  
„ Data interface to link-layer controller provided  
through 2/4/8 parallel lines at 50 Mbits/s.  
„ 25 MHz crystal oscillator and PLL provide a  
50 MHz link-layer controller clock as well as trans-  
mit/receive data at 100 Mbits/s, 200 Mbits/s, and  
400 Mbits/s.  
— Automatic microlow-power sleep mode during  
suspend.  
„ Multiple separate package signals provided for  
analog and digital supplies and grounds.  
„ Interface to link-layer controller supports Annex J  
electrical isolation as well as bus-keeper isolation.  
Description  
Features  
The Agere Systems FW801BF device provides the  
analog physical layer functions needed to imple-  
ment a one-port node in a cable-based IEEE 1394-  
1995 and IEEE 1394a-2000 network.  
„ Provides one fully compliant cable port at  
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.  
„ Fully supports 1394 Open HCI requirements.  
„ Supports arbitrated short bus reset to improve  
The cable port incorporates two differential line trans-  
ceivers. The transceivers include circuitry to monitor  
the line conditions as needed for determining con-  
nection status, for initialization and arbitration, and  
for packet reception and transmission. The PHY is  
designed to interface with a link-layer controller  
(LLC).  
utilization of the bus.  
„ Supports ack-accelerated arbitration and fly-by con-  
catenation.  
„ Supports connection debounce.  
„ Supports multispeed packet concatenation.  
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