Datasheet > 微控制器和处理器 > 时钟发生器> FS6131-01TR

FS6131-01TR

更新时间： 2024-01-02 16:59:09

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器光电二极管
页数	文件大小	规格书
44页	757K
描述
IC,MISCELLANEOUS CLOCK GENERATOR,CMOS,SOP,16PIN,PLASTIC

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技术参数
数据手册

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FS6131-01TR 技术参数

生命周期：	Transferred	包装说明：	SOP, SOP16,.25
Reach Compliance Code：	unknown	风险等级：	5.8
JESD-30 代码：	R-PDSO-G16	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6131-01TR 数据手册

FS6131

Reference

Divider (N_R)

Phase

Frequency

Detect

f_IN

Post

Divider (N_F)

VCO

f_OUT

f_VCO

f_IN

f_VCO

f_OUT

Feedback

Divider (N_F)

Figure 6: PLL with Post Divider

4.2.1. Clock Gobbler (Phase Adjust)

The clock gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the

CLKP/CLKN output clock phase relative to the REF input. The clock gobbler circuit removes a VCO clock pulse before the pulse clocks

the post divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase.

To adjust the phase relationship, switch the feedback divider source to the post divider input via the FBKDSRC bit, and toggle the GBL

register bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.

4.2.2. Phase Alignment

To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The

source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider

must be dividing at a multiple of the post divider.

Reference

Divider (N_R)

Phase

Frequency

Detect

f_IN

Post

Divider (N_F)

VCO

f_OUT

f_IN

Feedback

Divider (N_F)

f_OUT

Figure 7: Aligned I/O Phase

4.2.3. Phase Sampling and Initial Alignment

However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the

initial synchronization of the output phase to input phase, a phase align "flag" makes a transition (zero to one or one to zero) when the

output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input

clock phase.

Rev. 4 | Page 6 of 44 | www.onsemi.com

1...3 4 567 8 9...44

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