Datasheet > 微控制器和处理器 > 时钟发生器> FS6131-01TR

FS6131-01TR

更新时间： 2024-01-09 17:55:24

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器光电二极管
页数	文件大小	规格书
44页	757K
描述
IC,MISCELLANEOUS CLOCK GENERATOR,CMOS,SOP,16PIN,PLASTIC

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

FS6131-01TR 技术参数

生命周期：	Transferred	包装说明：	SOP, SOP16,.25
Reach Compliance Code：	unknown	风险等级：	5.8
JESD-30 代码：	R-PDSO-G16	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6131-01TR 数据手册

FS6131

4.0 Functional Block Description

4.1 Main Loop PLL

The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Error!

Reference source not found., the ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an

internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider.

During operation, the reference frequency (f^REF), generated by either the on-board crystal oscillator or an external frequency source, is

first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as N

the reference divider. The divided reference is then fed into the PFD.

for

The PFD controls the frequency of the VCO (f^VCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise,

continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback

divider (the modulus is denoted by N ) to close the loop.

The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at

the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is

f_VCO

N_F

f_REF

N_R

If the VCO frequency is used as the PLL output frequency (fCLK) then the basic PLL equation can be rewritten as

⎛

⎞

N_F

N_R

⎜

⎟

f_CLK= f_REF

⎝

⎠

4.1.1. Reference Divider

The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output)

or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and

can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.

4.1.2. Feedback Divider

The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully

programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also

called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO

can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall

power consumption of the divider.

For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective

modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-

frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider

moduli are generally undesirable due to increased phase jitter.

Rev. 4 | Page 3 of 44 | www.onsemi.com

1 234 5 6 7...44

下载PDF

与FS6131-01TR相关器件

型号	品牌	描述	获取价格	数据表
FS6182-01	ONSEMI	Clock Generator, CMOS, PDSO8,	获取价格
FS6183-03	AMI	Clock Generator, CMOS, PDSO8,	获取价格
FS6183-04	ONSEMI	24.576MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, SOIC-8	获取价格
FS6183-04	AMI	Clock Generator, 24.576MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8	获取价格
FS61857-01	AMI	Clock Driver, CMOS, PDSO48,	获取价格
FS6205-01	AMI	Clock Generator, 74.5808MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

FS6131-01TR

FS6131-01TR 技术参数

FS6131-01TR 数据手册

与FS6131-01TR相关器件

与FS6131-01TR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

FS6131-01TR

FS6131-01TR 技术参数

FS6131-01TR 数据手册

与FS6131-01TR相关器件

与FS6131-01TR相关文章

您还可以找

您在本页遇到什么问题？