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FS6131-01TR

更新时间： 2024-01-10 11:39:30

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器光电二极管
页数	文件大小	规格书
44页	757K
描述
IC,MISCELLANEOUS CLOCK GENERATOR,CMOS,SOP,16PIN,PLASTIC

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技术参数
数据手册

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FS6131-01TR 技术参数

生命周期：	Transferred	包装说明：	SOP, SOP16,.25
Reach Compliance Code：	unknown	风险等级：	5.8
JESD-30 代码：	R-PDSO-G16	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6131-01TR 数据手册

FS6131

4.1.4. Post Divider

The post divider consists of three individually programmable dividers, as shown in Error! Reference source not found..

POST1[1:0]

POST2[1:0]

POST3[1:0]

Post

Divider 1

(N_P1)

Post

Divider 2

(N_P2)

Post

Divider 3

(N_P3)

f_GBL

f_out

POST DIVIDER (N_Px

)

Figure 4: Post Divider

The moduli of the individual dividers are denoted as N_P1, N_P2, and N_P3, and together they make up the array modulus N_Px.

N_Px= N_P1× N_P2× N_P3

The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to

the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to

⎛

⎞⎛

⎞

N_F

⎜

⎟⎜

⎟

f_CLK= f_REF

N_RN_Px

⎝

⎠⎝

⎠

The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies

must be achieved exactly.

Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.

4.2 Phase Adjust and Sampling

In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock.

Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input

clock. Every cycle of the input clock equals N

R/N

cycles of the VCO clock.

Reference

Phase

f_IN

Divider (N_R)

Frequency

Detect

VCO

f_OUT

f_IN

Feedback

Divider (N_F)

f_OUT

Figure 5: Simple PLL

The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because

the post divider is outside the feedback loop.

Rev. 4 | Page 5 of 44 | www.onsemi.com

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