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FM25W256-GTR PDF预览

FM25W256-GTR

更新时间： 2024-02-06 04:22:06
品牌 Logo 应用领域
铁电 - RAMTRON 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
13页 293K
描述
256Kb Wide Voltage SPI F-RAM

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FM25W256-GTR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：SOP, SOP8,.25Reach Compliance Code：unknown
风险等级：5.88Is Samacsys：N
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
内存密度：262144 bit内存集成电路类型：NON-VOLATILE SRAM
内存宽度：8端子数量：8
字数：32768 words字数代码：32000
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：3/5 V认证状态：Not Qualified
最大待机电流：0.00015 A子类别：SRAMs
最大压摆率：0.007 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
Base Number Matches：1

FM25W256-GTR 数据手册

 浏览型号FM25W256-GTR的Datasheet PDF文件第2页浏览型号FM25W256-GTR的Datasheet PDF文件第3页浏览型号FM25W256-GTR的Datasheet PDF文件第4页浏览型号FM25W256-GTR的Datasheet PDF文件第6页浏览型号FM25W256-GTR的Datasheet PDF文件第7页浏览型号FM25W256-GTR的Datasheet PDF文件第8页 
FM25W256 - 256Kb SPI F-RAM  
WREN – Set Write Enable Latch  
The FM25W256 will power up with writes disabled.  
The WREN command must be issued prior to any  
write operation. Sending the WREN op-code will  
allow the user to issue subsequent op-codes for  
write operations. These include writing the status  
register and writing the memory.  
Power Up to First Access  
The FM25W256 is not accessible for a period of time  
(tPU) after power up. Users must comply with the  
timing parameter tPU, which is the minimum time  
from VDD (min) to the first /CS low.  
Data Transfer  
All data transfers to and from the FM25W256 occur  
in 8-bit groups. They are synchronized to the clock  
signal (SCK), and they transfer most significant bit  
(MSB) first. Serial inputs are registered on the rising  
edge of SCK. Outputs are driven from the falling  
edge of SCK.  
Sending the WREN op-code causes the internal  
Write Enable Latch to be set. A flag bit in the status  
register, called WEL, indicates the state of the latch.  
WEL=1 indicates that writes are permitted.  
Attempting to write the WEL bit in the status  
register has no effect on the state of this bit.  
Completing any write operation will automatically  
clear the write-enable latch and prevent further  
writes without another WREN command. Figure 5  
illustrates the WREN command bus configuration.  
Command Structure  
There are six commands called op-codes that can be  
issued by the bus master to the FM25W256. They are  
listed in the table below. These op-codes control the  
functions performed by the memory. They can be  
divided into three categories. First, there are  
commands that have no subsequent operations. They  
perform a single function such as to enable a write  
operation. Second are commands followed by one  
byte, either in or out. They operate on the status  
register. The third group includes commands for  
memory transactions followed by address and one or  
more bytes of data.  
WRDI – Write Disable  
The WRDI command disables all write activity by  
clearing the Write Enable Latch. The user can verify  
that writes are disabled by reading the WEL bit in  
the status register and verifying that WEL=0. Figure  
6 illustrates the WRDI command bus configuration.  
Table 1. Op-code Commands  
Name  
Description  
Op-code  
00000110b  
00000100b  
00000101b  
00000001b  
00000011b  
00000010b  
Set Write Enable Latch  
Write Disable  
WREN  
WRDI  
RDSR  
WRSR  
READ  
WRITE  
Read Status Register  
Write Status Register  
Read Memory Data  
Write Memory Data  
CS  
0
1
2
3
4
5
1
6
1
7
0
SCK  
SI  
0
0
0
0
0
Hi-Z  
SO  
Figure 5. WREN Bus Configuration  
Rev. 1.3  
Feb. 2011  
Page 5 of 13  
12345678...13

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