FM25W256-GTR

更新时间： 2024-01-08 12:48:34

品牌	Logo	应用领域
铁电 - RAMTRON		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
13页	293K
描述
256Kb Wide Voltage SPI F-RAM

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技术参数
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FM25W256-GTR 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP8,.25	Reach Compliance Code：	unknown
风险等级：	5.88	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
内存密度：	262144 bit	内存集成电路类型：	NON-VOLATILE SRAM
内存宽度：	8	端子数量：	8
字数：	32768 words	字数代码：	32000
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	32KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3/5 V	认证状态：	Not Qualified
最大待机电流：	0.00015 A	子类别：	SRAMs
最大压摆率：	0.007 mA	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

FM25W256-GTR 数据手册

FM25W256 - 256Kb SPI F-RAM

SCK

Hi-Z

Figure 6. WRDI Bus Configuration

RDSR – Read Status Register

WRSR – Write Status Register

The RDSR command allows the bus master to verify

the contents of the Status Register. Reading Status

provides information about the current state of the

write protection features. Following the RDSR op-

code, the FM25W256 will return one byte with the

contents of the Status Register. The Status Register is

described in detail in a later section.

The WRSR command allows the user to select

certain write protection features by writing a byte to

the Status Register. Prior to issuing a WRSR

command, the /WP pin must be high or inactive.

Prior to sending the WRSR command, the user must

send a WREN command to enable writes. Note that

executing a WRSR command is a write operation

and therefore clears the Write Enable Latch.

Figure 7. RDSR Bus Configuration

Figure 8. WRSR Bus Configuration

Table 2. Status Register

Status Register & Write Protection

BP1

BP0

Bit

The write protection features of the FM25W256 are

multi-tiered. Taking the /WP pin to a logic low state

is the hardware write protect function. All write

operations are blocked when /WP is low. To write the

memory with /WP high, a WREN op-code must first

be issued. Assuming that writes are enabled using

WREN and by /WP, writes to memory are controlled

by the Status Register. As described above, writes to

the status register are performed using the WRSR

command and subject to the /WP pin. The Status

WPEN

WEL

Name

Bits 0 and 4-6 are fixed at 0 and cannot be modified.

Note that bit 0 (Ready in EEPROMs) is unnecessary

as the F-RAM writes in real-time and is never busy.

The BP1 and BP0 control software write protection

features. They are nonvolatile (shaded yellow). The

WEL flag indicates the state of the Write Enable

Latch. Attempting to directly write the WEL bit in

the status register has no effect on its state. This bit

is internally set by the WREN command and cleared

Rev. 1.3

Feb. 2011

Page 6 of 13

1...3 4 567 8 9...13

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