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FM25VN05-GTR PDF预览

FM25VN05-GTR

更新时间： 2024-01-10 19:35:53
品牌 Logo 应用领域
铁电 - RAMTRON 存储
页数 文件大小 规格书
16页 334K
描述
512Kb Serial 3V F-RAM Memory

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FM25VN05-GTR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：unknown
HTS代码：8542.32.00.71风险等级：5.82
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm内存密度：524288 bit
内存集成电路类型：MEMORY CIRCUIT内存宽度：8
湿度敏感等级：1功能数量：1
端子数量：8字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm

FM25VN05-GTR 数据手册

 浏览型号FM25VN05-GTR的Datasheet PDF文件第3页浏览型号FM25VN05-GTR的Datasheet PDF文件第4页浏览型号FM25VN05-GTR的Datasheet PDF文件第5页浏览型号FM25VN05-GTR的Datasheet PDF文件第7页浏览型号FM25VN05-GTR的Datasheet PDF文件第8页浏览型号FM25VN05-GTR的Datasheet PDF文件第9页 
FM25V05 - 512Kb SPI FRAM  
to sending the WRSR command, the user must send  
a WREN command to enable writes. Note that  
executing a WRSR command is a write operation  
and therefore clears the Write Enable Latch. The bus  
configuration of RDSR and WRSR are shown  
below.  
WRSR – Write Status Register  
The WRSR command allows the user to select  
certain write protection features by writing a byte to  
the Status Register. Prior to issuing a WRSR  
command, the /W pin must be high or inactive. Prior  
S
C
D
Q
Figure 7. RDSR Bus Configuration  
S
C
D
Q
Figure 8. WRSR Bus Configuration  
no effect on its state. This bit is internally set and  
cleared via the WREN and WRDI commands,  
respectively.  
Status Register & Write Protection  
The write protection features of the FM25V05 are  
multi-tiered. Taking the /W pin to a logic low state is  
the hardware write-protect function. Status Register  
write operations are blocked when /W is low. To  
write the memory with /W high, a WREN op-code  
must first be issued. Assuming that writes are enabled  
using WREN and by /W, writes to memory are  
controlled by the Status Register. As described  
above, writes to the Status Register are performed  
using the WRSR command and subject to the /W pin.  
The Status Register is organized as follows.  
BP1 and BP0 are memory block write protection bits.  
They specify portions of memory that are write-  
protected as shown in the following table.  
Table 3. Block Memory Write Protection  
BP1  
BP0 Protected Address Range  
0
0
1
1
0
1
0
1
None  
C000h to FFFFh (upper ¼)  
8000h to FFFFh (upper ½)  
0000h to FFFFh (all)  
Table 2. Status Register  
7
6
1
5
0
4
0
3
BP1  
2
BP0  
1
0
0
Bit  
WPEN  
WEL  
Name  
The BP1 and BP0 bits and the Write Enable Latch  
are the only mechanisms that protect the memory  
from writes. The remaining write protection features  
protect inadvertent changes to the block protect bits.  
Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and  
none of these bits can be modified. Note that bit 0  
(“Ready” in Serial Flash) is unnecessary as the F-  
RAM writes in real-time and is never busy, so it  
reads out as a ‘0’. There is an exception to this when  
the device is waking up from Sleep Mode, which is  
described on the following page. The BP1 and BP0  
control software write protection features. They are  
nonvolatile (shaded yellow). The WEL flag indicates  
the state of the Write Enable Latch. Attempting to  
directly write the WEL bit in the Status Register has  
The WPEN bit controls the effect of the hardware /W  
pin. When WPEN is low, the /W pin is ignored.  
When WPEN is high, the /W pin controls write  
access to the Status Register. Thus the Status Register  
is write protected if WPEN=1 and /W=0.  
This scheme provides a write protection mechanism,  
which can prevent software from writing the memory  
Rev. 2.0  
May 2010  
Page 6 of 16  
1...3456789...16

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