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FIN1285MTDX PDF预览

FIN1285MTDX

更新时间: 2024-11-02 20:43:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
16页 485K
描述
Line Driver, 4 Func, 4 Driver, PDSO56, 6.10 MM, MO-153, TSSOP-48

FIN1285MTDX 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP56,.3,20针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
差分输出:YES驱动器位数:4
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G56
长度:14 mm功能数量:4
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
最大接收延迟:座面最大高度:1.1 mm
子类别:Line Driver or Receivers最大压摆率:66 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

FIN1285MTDX 数据手册

 浏览型号FIN1285MTDX的Datasheet PDF文件第2页浏览型号FIN1285MTDX的Datasheet PDF文件第3页浏览型号FIN1285MTDX的Datasheet PDF文件第4页浏览型号FIN1285MTDX的Datasheet PDF文件第5页浏览型号FIN1285MTDX的Datasheet PDF文件第6页浏览型号FIN1285MTDX的Datasheet PDF文件第7页 
Preliminary  
December 2003  
Revised December 2003  
FIN1287 FIN1288 •  
FIN1285 FIN1286  
LVDS 28-Bit Serializers/De-Serializers (Preliminary)  
General Description  
Features  
Low power consumption  
The FIN1287 and FIN1285 transform 28-bit wide parallel  
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low  
Voltage Differential Signaling) data streams. A phase-  
locked transmit clock is transmitted in parallel with the data  
steam over a separate LVDS link. Every cycle of transmit  
clock 28 bits of input LVTTL data are sampled and trans-  
mitted.  
20 MHz to 85 MHz shift clock support  
50% duty cycle on the clock output of receiver  
±1V common-mode range around 1.2V  
Narrow bus reduces cable size and cost  
High throughput (up to 2.38 Gbps throughput)  
Up to 595 Mbps per channel  
The FIN1288 and FIN1286 receive and convert the 4 serial  
LVDS data streams back into 28 bits of LVTTL data. Refer  
to Table 1 for a matrix summary of the Serializers and De-  
serializers available. For the FIN1287, at a transmit clock  
frequency of 85 MHz, 28 bits of LVTTL data are transmitted  
at a rate of 595 Mbps per LVDS channel.  
Internal PLL with no external component  
Compatible with TIA/EIA-644 specification  
Devices are offered in 56-lead TSSOP packages  
These chipsets are an ideal solution to solve EMI and  
cable size problems associated with wide and high-speed  
TTL interfaces.  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1285MTD  
(Preliminary)  
MTD56  
MTD56  
MTD56  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
FIN1286MTD  
(Preliminary)  
FIN1287MTD  
(Preliminary)  
FIN1288MTD  
(Preliminary)  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
© 2003 Fairchild Semiconductor Corporation  
DS500868  
www.fairchildsemi.com  

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