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FIN1286MTD

更新时间： 2024-11-02 20:43:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管接口集成电路
页数 文件大小 规格书
16页 485K
描述
Line Receiver, 4 Func, 4 Rcvr, PDSO56, 6.10 MM, MO-153, TSSOP-48

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中文翻译

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FIN1286MTD 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G56
长度：14 mm功能数量：4
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3 V认证状态：Not Qualified
最大接收延迟：接收器位数：4
座面最大高度：1.1 mm子类别：Line Driver or Receivers
最大压摆率：135 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

FIN1286MTD 数据手册

 浏览型号FIN1286MTD的Datasheet PDF文件第2页浏览型号FIN1286MTD的Datasheet PDF文件第3页浏览型号FIN1286MTD的Datasheet PDF文件第4页浏览型号FIN1286MTD的Datasheet PDF文件第5页浏览型号FIN1286MTD的Datasheet PDF文件第6页浏览型号FIN1286MTD的Datasheet PDF文件第7页 
Preliminary  
December 2003  
Revised December 2003  
FIN1287 • FIN1288 •  
FIN1285 • FIN1286  
LVDS 28-Bit Serializers/De-Serializers (Preliminary)  
General Description  
Features  
■ Low power consumption  
The FIN1287 and FIN1285 transform 28-bit wide parallel  
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low  
Voltage Differential Signaling) data streams. A phase-  
locked transmit clock is transmitted in parallel with the data  
steam over a separate LVDS link. Every cycle of transmit  
clock 28 bits of input LVTTL data are sampled and trans-  
mitted.  
■ 20 MHz to 85 MHz shift clock support  
■ 50% duty cycle on the clock output of receiver  
■ ±1V common-mode range around 1.2V  
■ Narrow bus reduces cable size and cost  
■ High throughput (up to 2.38 Gbps throughput)  
■ Up to 595 Mbps per channel  
The FIN1288 and FIN1286 receive and convert the 4 serial  
LVDS data streams back into 28 bits of LVTTL data. Refer  
to Table 1 for a matrix summary of the Serializers and De-  
serializers available. For the FIN1287, at a transmit clock  
frequency of 85 MHz, 28 bits of LVTTL data are transmitted  
at a rate of 595 Mbps per LVDS channel.  
■ Internal PLL with no external component  
■ Compatible with TIA/EIA-644 specification  
■ Devices are offered in 56-lead TSSOP packages  
These chipsets are an ideal solution to solve EMI and  
cable size problems associated with wide and high-speed  
TTL interfaces.  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1285MTD  
(Preliminary)  
MTD56  
MTD56  
MTD56  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
FIN1286MTD  
(Preliminary)  
FIN1287MTD  
(Preliminary)  
FIN1288MTD  
(Preliminary)  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
© 2003 Fairchild Semiconductor Corporation  
DS500868  
www.fairchildsemi.com  
1234567...16

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FIN12AC FAIRCHILD

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 		Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (
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 		uSerDes Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency
FIN12AC_08 FAIRCHILD

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FIN12ACMLX FAIRCHILD

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