www.fairchildsemi.com
AN-6006
FAN5068 Component calculation and
simulation tools
Background / Overview
To simplify designs using the FAN5068 DDR/ACPI control IC, Fairchild provides:
•
An Excel workbook to calculate recommended external component values
and
•
A continuous time behavioral model of the modulator that runs in PSPICE A/D v 9.1 or above. The model is
small enough to run under Cadence's Orcad Lite Edition (includes Orcad Capture and PSPICE A/D), which can
be ordered on CD or may be downloaded at:
http://www.orcad.com/downloads/demo/default.asp
Information on the FAN5068, including the datasheet can be found on:
http://www.fairchildsemi.com/pf/FA/FAN5068.html
This package of design aids (including this document) is can be downloaded from:
http://www.fairchildsemi.com/collateral/AN-6006.zip.
To install, copy AN-6006.ZIP to an empty folder (e.g. “FAN5068Design”). Then unzip AN-6006.ZIP into that
folder.
Recommended design procedure:
1. Use the spreadsheet (FAN5068 Design calculation aid.xls ) to calculate the output filter using the “Output
Filter” tab.
2. Use the “Main Sheet” tab of the spreadsheet to calculate the other component values once you have selected the
output L and C.
3. Use the “Compensation” tab to design the compensation network.
4. Input the values you have selected into the PSPICE model. Generate a Bode plot by simulating with the
“application circuit-ac sweep” simulation profile. Make sure to simulate over the corners of VIN and IOUT for
your application.
5. Once you are satisfied with the small signal stability, you can view the transient response by simulating using
the “application circuit-transient response” simulation profile. Be sure the follow the instructions at the bottom
of the Application Circuit, Page 1 sheet for resetting RLOAD before simulating transient response.
Design Calculation Spreadsheet: FAN5068 Design calculation aid.xls
For instructions on the use of this spreadsheet, see the “Instructions” tab of the spreadsheet.
PSPICE Simulation Model
The simulation model is a sampled data continuous time model, which is adapted from Ray Ridley and Dennis
Feucht's modeling work for current mode controllers1 2 3. It is set up to provide a bode plot where the red trace is
Phase Margin (in degrees) and the green trace is gain (in dB). For stable response, we recommend at least 45° of
phase margin when the gain crosses 0dB. The model also provides transient response using a pulsed current source
,
,
(I1) as the load. The IC’s error-amp behavioral model is based on Ray Kendall’s Macromodelling article in EDN. 4
To run the model start Capture (9.1 or higher), open FAN5068.opj (this is the "project" file for Capture). Double
click on Page 1 Under .\fan5068.dsn\Application Circuit.
REV. 1.0.0 05/26/04