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FAN5068MPX PDF预览

FAN5068MPX

更新时间: 2024-01-14 05:14:42
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 调节器双倍数据速率
页数 文件大小 规格书
18页 160K
描述
DDR-1/DDR-2 plus ACPI Regulator Combo

FAN5068MPX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC24,.19SQ,25
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.65其他特性:ALSO OPERATES AT 3.3 VOLT OUTPUT
模拟集成电路 - 其他类型:SWITCHING CONTROLLER控制模式:CURRENT-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:5.5 V
最小输入电压:4.5 V标称输入电压:5 V
JESD-30 代码:S-XQCC-N24JESD-609代码:e4
长度:5 mm湿度敏感等级:1
功能数量:1端子数量:24
最高工作温度:85 °C最低工作温度:-10 °C
最大输出电流:1.5 A标称输出电压:1.2 V
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.19SQ,25封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Switching Regulator or Controllers表面贴装:YES
切换器配置:PUSH-PULL最大切换频率:345 kHz
温度等级:OTHER端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmBase Number Matches:1

FAN5068MPX 数据手册

 浏览型号FAN5068MPX的Datasheet PDF文件第2页浏览型号FAN5068MPX的Datasheet PDF文件第3页浏览型号FAN5068MPX的Datasheet PDF文件第4页浏览型号FAN5068MPX的Datasheet PDF文件第5页浏览型号FAN5068MPX的Datasheet PDF文件第6页浏览型号FAN5068MPX的Datasheet PDF文件第7页 
www.fairchildsemi.com  
FAN5068  
DDR-1/DDR-2 plus ACPI Regulator Combo  
Features  
General Description  
• PWM regulator for VDDQ (2.5V or 1.8V)  
• Linear LDO regulator generates VTT = VDDQ/2, 1.5A  
Peak sink/source capability  
• 1 independent programable ULDO controllers driving  
external N-Channel MOSFET  
• ACPI drive and control for 5V DUAL generation  
• 3.3V Internal LDO for 3V-ALW generation  
• 300kHz fixed frequency switching  
• RDS(ON) current sensing or optional current sense resistor  
for precision over-current detect  
The FAN5068 DDR memory regulator combines a high-  
efficiency PWM controller to generate the supply voltage,  
VDDQ, and a linear regulator to generate VTT, the termina-  
tion voltage. Synchronous rectification provides high-  
efficiency over a wide range of load currents. Efficiency is  
further enhanced by using the low-side MOSFET’s RDS(ON)  
to sense current instead of a series sense resistor.  
In S3 mode, only the VDDQ switcher and the 3.3V regula-  
tors remain on while the VTT and ULDO regulators are shut  
off. To avoid "glitching" the VDDQ output during the transi-  
tion from S3 to S0, the three linear regulators use the SS  
capacitor to limit their slew rates, thereby limiting the surge  
current from the VDDQ output. PGOOD becomes true in S0  
only when all 3 regulators have achieved stable outputs.  
• Internal Synchronous Boot diode  
• Power Good signal for all voltages  
• Input Under-Voltage Lock-Out (UVLO)  
• Thermal Shutdown  
• Latched Multi-Fault Protection  
• 24-pin 5x5mm MLP package  
In S5 (EN = 0), the 3.3V internal LDO stays on, while the  
other regulators are powered down.  
Applications  
• DDR-1/DDR-2 VDDQ and VTT voltage generation with  
The VDDQ PWM regulator is a sampled current mode con-  
trol with external compensation to achieve fast load transient  
response and provide system design optimization.  
ACPI support  
• Desktop PC's  
• Servers  
The VTT regulator derives its reference and takes its power  
from the VDDQ PWM regulator output using a precision  
internal voltage divider to set its output at 1/2 of VDDQ. The  
VTT termination regulator is capable of sourcing or sinking  
at least 1.5A peak current.  
REV. 1.0.1 9/9/04  

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