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F280041CPZQR PDF预览

F280041CPZQR

更新时间: 2024-09-15 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 时钟微控制器外围集成电路闪存
页数 文件大小 规格书
230页 6260K
描述
具有 100MHz 频率、FPU、TMU、128KB 闪存、InstaSPIN-FOC、CLB、PGA、SDFM 的汽车类 C2000™ 32 位 MCU | PZ | 100 | -40 to 125

F280041CPZQR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LQFP-100
Reach Compliance Code:compliantFactory Lead Time:6 weeks
风险等级:2.28Samacsys Description:32-bit Microcontrollers - MCU PiccoloG 32-bit MCU with 100 MHz, FPU, TMU, 128 KB Flash, InstaSPIN-FOC, CLB, PGAs, SDFM 100-LQFP -40 to 125
具有ADC:YES地址总线宽度:
位大小:32最大时钟频率:100 MHz
DAC 通道:YESDMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PQFP-G100
JESD-609代码:e4长度:14 mm
湿度敏感等级:3DMA 通道数量:6
I/O 线路数量:40端子数量:100
片上程序ROM宽度:16最高工作温度:125 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260RAM(字节):102400
ROM(单词):65536ROM可编程性:FLASH
筛选级别:AEC-Q100座面最大高度:1.6 mm
速度:100 MHz最大供电电压:1.32 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

F280041CPZQR 数据手册

 浏览型号F280041CPZQR的Datasheet PDF文件第2页浏览型号F280041CPZQR的Datasheet PDF文件第3页浏览型号F280041CPZQR的Datasheet PDF文件第4页浏览型号F280041CPZQR的Datasheet PDF文件第5页浏览型号F280041CPZQR的Datasheet PDF文件第6页浏览型号F280041CPZQR的Datasheet PDF文件第7页 
TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,  
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C  
SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021  
TMS320F28004x Microcontrollers  
– Embedded Real-time Analysis and Diagnostic  
(ERAD)  
Communications peripherals  
– One Power-Management Bus (PMBus)  
interface  
1 Features  
TMS320C28x 32-bit CPU  
– 100 MHz  
– IEEE 754 single-precision Floating-Point Unit  
(FPU)  
– One Inter-integrated Circuit (I2C) interface  
(pin-bootable)  
– Trigonometric Math Unit (TMU)  
3×-cycle to 4×-cycle improvement for  
common trigonometric functions versus  
software libraries  
– Two Controller Area Network (CAN) bus ports  
(pin-bootable)  
– Two Serial Peripheral Interface (SPI) ports  
(pin-bootable)  
13-cycle Park transform  
– Viterbi/Complex Math Unit (VCU-I)  
Ten hardware breakpoints (with ERAD)  
Programmable Control Law Accelerator (CLA)  
– 100 MHz  
– IEEE 754 single-precision floating-point  
instructions  
– Two Serial Communication Interfaces (SCIs)  
(pin-bootable)  
– One Local Interconnect Network (LIN)  
– One Fast Serial Interface (FSI) with a  
transmitter and receiver  
Analog system  
– Three 3.45-MSPS, 12-bit Analog-to-Digital  
Converters (ADCs)  
– Executes code independently of main CPU  
On-chip memory  
Up to 21 external channels  
Four integrated post-processing blocks  
(PPBs) per ADC  
– 256KB (128KW) of flash (ECC-protected)  
across two independent banks  
– 100KB (50KW) of RAM (ECC-protected or  
parity-protected)  
– Dual-zone security supporting third-party  
development  
– Seven windowed comparators (CMPSS) with  
12-bit reference Digital-to-Analog Converters  
(DACs)  
Digital glitch filters  
– Unique Identification (UID) number  
Clock and system control  
– Two 12-bit buffered DAC outputs  
– Seven Programmable Gain Amplifiers (PGAs)  
– Two internal zero-pin 10-MHz oscillators  
– On-chip crystal oscillator and external clock  
input  
Programmable gain settings: 3, 6, 12, 24  
Programmable output filtering  
– Windowed watchdog timer module  
– Missing clock detection circuitry  
1.2-V core, 3.3-V I/O design  
– Internal VREG or DC-DC for 1.2-V generation  
allows for single-supply designs  
– Brownout reset (BOR) circuit  
System peripherals  
Enhanced control peripherals  
– 16 ePWM channels with high-resolution  
capability (150-ps resolution)  
Integrated dead-band support with high  
resolution  
Integrated hardware trip zones (TZs)  
– Seven Enhanced Capture (eCAP) modules  
High-resolution Capture (HRCAP) available  
on two modules  
– 6-channel Direct Memory Access (DMA)  
controller  
– Two Enhanced Quadrature Encoder Pulse  
(eQEP) modules with support for CW/CCW  
operation modes  
– Four Sigma-Delta Filter Module (SDFM) input  
channels (two parallel filters per channel)  
– 40 individually programmable multiplexed  
General-Purpose Input/Output (GPIO) pins  
– 21 digital inputs on analog pins  
– Enhanced Peripheral Interrupt Expansion  
(ePIE) module  
Standard SDFM data filtering  
Comparator filter for fast action for  
overvalue or undervalue condition  
– Multiple low-power mode (LPM) support with  
external wakeup  
Configurable Logic Block (CLB)  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 

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