Datasheet > EPX8160QC208-12

EPX8160QC208-12

更新时间： 2024-11-11 19:32:39

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EPX8160QC208-12 数据手册

FLASHlogic

Programmable Logic

Device Family

June 1996, ver. 2

Data Sheet

■

High-performance programmable logic device (PLD) family

Features...

–

SRAM-based logic with shadow FLASH memory elements

fabricated on advanced CMOS technology

–

Logic densities from 1,600 to 3,200 usable gates (see Table 1)

Combinatorial speeds with t as low as 10 ns

Counter frequencies of up to 80 MHz

■

8 to 16 logic array blocks (LABs) linked by a 100%-connectable

programmable interconnect array (PIA) for improved fitting of

complex designs

24V10 macrocell features available

–

Dual feedback on all I/O pins

Product-term allocation matrix supporting up to 16 product

terms per macrocell

–

Programmable registers providing D, T, SR, and JK flipflop

functionality with clear, preset, and clock controls

Fast 12-bit identity compare option

■

Fully compliant with PCI Local Bus Specification, version 2.1

Table 1. FLASHlogic Device Features

Feature

EPX880

EPX8160

Usable gates

1,600

10,240

3,200

Maximum SRAM bits

Macrocells

20,480

160

Logic array blocks (LABs)

Package options

84-pin PLCC (62)

208-pin PQFP (172)

(maximum user I/O pins)

132-pin PQFP (104)

(ns)

(MHz)

CNT

Altera Corporation

265

A-DS-FLSH-02

12 3 4 5 6 7...44

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