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EPXA10 PDF预览

EPXA10

更新时间: 2024-11-11 06:57:47
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
16页 291K
描述
Excalibur Device Overview

EPXA10 数据手册

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Excalibur Device Overview  
May 2002, ver. 2.0  
Data Sheet  
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Combination of a world-class RISC processor system with industry-  
leading programmable logic on a single device  
Industry-standard ARM922T32-bit RISC processor core operating  
at up to 200 MHz  
Features...  
ARMv4T instruction set with Thumb® extensions  
Memory management unit (MMU) included for real-time  
operating system (RTOS) support  
Harvard cache architecture with 64-way set associative separate  
8-Kbyte instruction and 8-Kbyte data caches  
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APEX20KE-like programmable logic architecture ranging from  
100,000 to 1,000,000 gates (see Table 1 on page 3)  
Advanced bus architecture based on advanced microcontroller bus  
architecture (AMBA) high-performance bus (AHB)  
Embedded programmable on-chip peripherals  
ETM9 embedded trace module to assist software debugging  
Flexible interrupt controller  
Universal asynchronous receiver/transmitter (UART)  
General-purpose timer  
Watchdog timer  
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Advanced memory support  
Internal single-port SRAM up to 256 Kbytes  
Internal dual-port SRAM up to 128 Kbytes  
Internal SDRAM controller  
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Single data-rate (SDR) and double data-rate (DDR) support  
Up to 512 Mbytes  
Data rates to 133 (266) MHz  
Expansion bus interface (EBI)  
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Compatible with industry-standard flash memory, SRAMs,  
and peripheral devices  
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Four devices, each up to 32 Mbytes  
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PLD configuration/reconfiguration possible via the embedded  
processor software  
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Altera Corporation  
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DS-EXCARM-2.0  

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