Datasheet > EPM9560

EPM9560

更新时间： 2024-11-05 06:57:47

品牌	Logo	应用领域
阿尔特拉 - ALTERA		可编程逻辑器件
页数	文件大小	规格书
46页	495K
描述
Programmable Logic Device Family

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EPM9560 数据手册

MAX 9000

Programmable Logic

Device Family

Includes

MAX 9000A

June 2003, ver. 6.5

Data Sheet

■

High-performance CMOS EEPROM-based programmable logic

devices (PLDs) built on third-generation Multiple Array MatriX

(MAX^®) architecture

Features...

■

5.0-V in-system programmability (ISP) through built-in IEEE Std.

1149.1 Joint Test Action Group (JTAG) interface

Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE

Std. 1149.1-1990

High-density erasable programmable logic device (EPLD) family

ranging from 6,000 to 12,000 usable gates (see Table 1)

10-ns pin-to-pin logic delays with counter frequencies of up to

144 MHz

Fully compliant with the peripheral component interconnect Special

Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2

Dual-output macrocell for independent use of combinatorial and

registered logic

■

FastTrack^®Interconnect for fast, predictable interconnect delays

Input/ output registers with clear and clock enable on all I/ O pins

Programmable output slew-rate control to reduce switching noise

MultiVolt^™I/ O interface operation, allowing devices to interface with

3.3-V and 5.0-V devices

■

Configurable expander product-term distribution allowing up to 32

product terms per macrocell

Programmable power-saving mode for more than 50% power

reduction in each macrocell

Table 1. MAX 9000 Device Features

Feature EPM9320

EPM9400

EPM9480

EPM9560

EPM9320A

EPM9560A

Usable gates

6,000

484

320

8,000

580

400

10,000

676

480

12,000

772

560

Flipflops

Macrocells

Logic array blocks (LABs)

Maximum user I/O pins

t_PD1(ns)

168

159

175

216

t_FSU(ns)

3.0

_FCO(ns)

4.5

4.8

f_CNT(MHz)

144

118

144

Altera Corporation

DS-M9000-6.5

12 3 4 5 6 7...46

中文翻译

下载PDF

与EPM9560相关器件

型号	品牌	获取价格	描述	数据表
EPM9560A	ALTERA	获取价格	Programmable Logic Device Family
EPM9560ABC356-10	ETC	获取价格
EPM9560ABC356-15	ALTERA	获取价格	EE PLD, 16.6ns, CMOS, PBGA356, HEAT SINK, BGA-356
EPM9560ABI356-10	ETC	获取价格
EPM9560ARC208-10	ETC	获取价格
EPM9560ARC208-10C	ALTERA	获取价格	EE PLD, 11.4ns, CMOS, PQFP208, 30.60 X 30.60 MM, 0.50 MM PITCH, POWER, RQFP-208
EPM9560ARC208-10N	ALTERA	获取价格	EE PLD, 11.4ns, CMOS, PQFP208, POWER, RQFP-208
EPM9560ARC208-15C	ALTERA	获取价格	EE PLD, 16.6ns, CMOS, PQFP208, HEAT SINK, POWER, QFP-208
EPM9560ARC240-10	ETC	获取价格
EPM9560ARC240-10C	ALTERA	获取价格	EE PLD, 11.4ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, POWER, RQFP-240