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EPM9560RC208-15 PDF预览

EPM9560RC208-15

更新时间: 2024-11-04 23:51:15
品牌 Logo 应用领域
其他 - ETC 可编程逻辑输入元件LTE时钟
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42页 459K
描述

EPM9560RC208-15 数据手册

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MAX 9000  
Programmable Logic  
Device Family  
Includes  
MAX 9000A  
®
November 2001, ver. 6.3  
Data Sheet  
High-performance CMOS EEPROM-based programmable logic  
devices (PLDs) built on third-generation Multiple Array MatriX  
(MAX®) architecture  
Features...  
5.0-V in-system programmability (ISP) through built-in IEEE Std.  
1149.1 Joint Test Action Group (JTAG) interface  
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE  
Std. 1149.1-1990  
High-density erasable programmable logic device (EPLD) family  
ranging from 6,000 to 12,000 usable gates (see Table 1)  
10-ns pin-to-pin logic delays with counter frequencies of up to  
144 MHz  
Fully compliant with the peripheral component interconnect Special  
Interest Groups (PCI SIG) PCI Local Bus Specification, Revision 2.2  
Dual-output macrocell for independent use of combinatorial and  
registered logic  
FastTrack® Interconnect for fast, predictable interconnect delays  
Input/ output registers with clear and clock enable on all I/ O pins  
Programmable output slew-rate control to reduce switching noise  
MultiVoltI/ O interface operation, allowing devices to interface  
with 3.3-V and 5.0-V devices  
Configurable expander product-term distribution allowing up to 32  
product terms per macrocell  
Programmable power-saving mode for more than 50% power  
reduction in each macrocell  
Table 1. MAX 9000 Device Features  
Feature EPM9320  
EPM9400  
EPM9480  
EPM9560  
EPM9320A  
EPM9560A  
Usable gates  
6,000  
484  
320  
20  
8,000  
580  
400  
25  
10,000  
676  
480  
30  
12,000  
772  
560  
35  
Flipflops  
Macrocells  
Logic array blocks (LABs)  
Maximum user I/O pins  
tPD1 (ns)  
168  
10  
159  
15  
175  
10  
216  
10  
tFSU (ns)  
3.0  
5
3.0  
3.0  
t
FCO (ns)  
4.5  
7
4.8  
4.8  
fCNT (MHz)  
144  
118  
144  
144  
Altera Corporation  
1
A-DS-M9000-6.3  

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