Datasheet > EPM7256BQI208-10

EPM7256BQI208-10

更新时间： 2023-01-03 02:45:13

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
66页	962K
描述
EE PLD, 10ns, 256-Cell, CMOS, PQFP208, PLASTIC, QFP-208

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MAX 7000B Programmable Logic Device Data Sheet

Macrocells

The MAX 7000B macrocell can be individually configured for either

sequential or combinatorial logic operation. The macrocell consists of

three functional blocks: the logic array, the product-term select matrix,

and the programmable register. Figure 2 shows the MAX 7000B

macrocell.

Figure 2. MAX 7000B Macrocell

Global Global

LAB Local Array

Clear

Clocks

From

I/O pin

Parallel Logic

Expanders

(from other

macrocells)

Fast Input

Select

Programmable

Bypass

To I/O

Control

Block

PRN

D/T

Clock/

Enable

Select

Product-

Term

Select

Matrix

ENA

CLRN

VCC

Clear

Select

To PIA

Shared Logic

Expanders

36 Signals

from PIA

16 Expander

Product Terms

Combinatorial logic is implemented in the logic array, which provides

five product terms per macrocell. The product-term select matrix allocates

these product terms for use as either primary logic inputs (to the ORand

XORgates) to implement combinatorial functions, or as secondary inputs

to the macrocell’s register preset, clock, and clock enable control

functions.

Two kinds of expander product terms (“expanders”) are available to

supplement macrocell logic resources:

■

Shareable expanders, which are inverted product terms that are fed

back into the logic array

Parallel expanders, which are product terms borrowed from adjacent

macrocells

Altera Corporation

1...4 5 678 9 10...66

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