Datasheet > EPM7256BQI208-10

EPM7256BQI208-10

更新时间： 2023-01-03 02:45:13

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
66页	962K
描述
EE PLD, 10ns, 256-Cell, CMOS, PQFP208, PLASTIC, QFP-208

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EPM7256BQI208-10 数据手册

MAX 7000B Programmable Logic Device Data Sheet

Figure 1. MAX 7000B Device Block Diagram

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 or 10 Output Enables (1)

LAB A

LAB B

2 to 16

Macrocells

1 to 16

Macrocells

17 to 32

I/O

2 to 16 I/O

Control

Block

Control

Block

2 to 16 I/O

6 or 10

2 to 16

6 or 10

LAB C

LAB D

2 to 16

PIA

2 to 16

Macrocells

33 to 48

Macrocells

49 to 64

I/O

Control

Block

I/O

Control

Block

2 to 16 I/O

6 or 10

2 to 16

Note:

(1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten

output enables.

Logic Array Blocks

The MAX 7000B device architecture is based on the linking of

high-performance LABs. LABs consist of 16 macrocell arrays, as shown in

Figure 1. Multiple LABs are linked together via the PIA, a global bus that

is fed by all dedicated input pins, I/O pins, and macrocells.

Each LAB is fed by the following signals:

■

36 signals from the PIA that are used for general logic inputs

Global controls that are used for secondary register functions

Direct input paths from I/O pins to the registers that are used for fast

setup times

Altera Corporation

1...3 4 567 8 9...66

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