Datasheet > EPM7256BQI208-10

EPM7256BQI208-10

更新时间： 2023-01-03 02:45:13

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
66页	962K
描述
EE PLD, 10ns, 256-Cell, CMOS, PQFP208, PLASTIC, QFP-208

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EPM7256BQI208-10 数据手册

MAX 7000B Programmable Logic Device Data Sheet

Table 3. MAX 7000B Maximum User I/O Pins

Note (1)

Device

44-Pin 44-Pin 48-Pin 49-Pin

PLCC TQFP TQFP 0.8-mm

100-

TQFP

100-Pin

FineLine

BGA (4)

144- 169-Pin 208-

256- 256-Pin

Pin FineLine

BGA BGA (4)

TQFP

0.8-mm

Ultra

PQFP

(2)

Ultra

FineLine

BGA (3)

FineLine

BGA (3)

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

100

120

100

141

100

164

176

212

Notes:

(1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O

pins become JTAG pins.

(2) Contact Altera for up-to-date information on available device package options.

(3) All 0.8-mm Ultra FineLine BGA packages are footprint-compatible via the SameFrame^TMpin-out feature. Therefore,

designers can design a board to support a variety of devices, providing a flexible migration path across densities

and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on

page 14 for more details.

(4) All FineLine BGA packages are footprint-compatible via the SameFrame pin-out feature. Therefore, designers can

design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.

Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 14 for more

details.

MAX 7000B devices use CMOS EEPROM cells to implement logic

functions. The user-configurable MAX 7000B architecture accommodates

a variety of independent combinatorial and sequential logic functions.

The devices can be reprogrammed for quick and efficient iterations

during design development and debug cycles, and can be programmed

and erased up to 100 times.

MAX 7000B devices contain 32 to 512 macrocells that are combined into

groups of 16 macrocells, called logic array blocks (LABs). Each macrocell

has a programmable-AND/fixed-ORarray and a configurable register with

independently programmable clock, clock enable, clear, and preset

functions. To build complex logic functions, each macrocell can be

supplemented with both shareable expander product terms and high-

speed parallel expander product terms to provide up to 32 product terms

per macrocell.

Altera Corporation

1 2 345 6 7...66

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