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EPM7256BUC169-5N PDF预览

EPM7256BUC169-5N

更新时间: 2023-02-26 13:40:38
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑器件
页数 文件大小 规格书
76页 1516K
描述
EE PLD, 5ns, 256-Cell, CMOS, PBGA169, 0.8 MM, UBGA-169

EPM7256BUC169-5N 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA49,7X7,32
针数:49Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:N其他特性:YES
最大时钟频率:303 MHz系统内可编程:YES
JESD-30 代码:S-PBGA-B49JESD-609代码:e1
JTAG BST:YES长度:7 mm
专用输入次数:I/O 线路数量:36
宏单元数:32端子数量:49
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 36 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA49,7X7,32封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8/3.3,2.5 V可编程逻辑类型:EE PLD
传播延迟:3.5 ns认证状态:Not Qualified
座面最大高度:1.55 mm子类别:Programmable Logic Devices
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:7 mm
Base Number Matches:1

EPM7256BUC169-5N 数据手册

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MAX 7000B  
Programmable Logic  
Device  
®
September 2005, ver. 3.5  
Data Sheet  
High-performance 2.5-V CMOS EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
Features...  
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V  
MAX 7000A device families  
High-density PLDs ranging from 600 to 10,000 usable gates  
3.5-ns pin-to-pin logic delays with counter frequencies in excess  
of 303.0 MHz  
Advanced 2.5-V in-system programmability (ISP)  
Programs through the built-in IEEE Std. 1149.1 Joint Test Action  
Group (JTAG) interface with advanced pin-locking capability  
Enhanced ISP algorithm for faster programming  
ISP_Done bit to ensure complete programming  
Pull-up resistor on I/O pins during in-system programming  
ISP circuitry compliant with IEEE Std. 1532  
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V  
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.  
f
Table 1. MAX 7000B Device Features  
Feature  
EPM7032B  
EPM7064B  
EPM7128B  
EPM7256B  
EPM7512B  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
36  
68  
100  
164  
212  
t
PD (ns)  
SU (ns)  
3.5  
2.1  
3.5  
2.1  
4.0  
2.5  
5.0  
3.3  
5.5  
3.6  
t
tFSU (ns)  
CO1 (ns)  
1.0  
1.0  
1.0  
1.0  
1.0  
t
2.4  
2.4  
2.8  
3.3  
3.7  
fCNT (MHz)  
303.0  
303.0  
243.9  
188.7  
163.9  
Altera Corporation  
1
DS-MAX7000B-3.5  

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