Datasheet > EPM7256E

EPM7256E

更新时间： 2024-02-11 07:19:33

品牌	Logo	应用领域
阿尔特拉 - ALTERA		可编程逻辑器件
页数	文件大小	规格书
62页	1087K
描述
Programmable Logic Device Family

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EPM7256E 数据手册

MAX 7000

Programmable Logic

Device Family

December 2002, ver. 6.5

Data Sheet

■

High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX^®architecture

5.0-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in

MAX 7000S devices

Features...

–

ISP circuitry compatible with IEEE Std. 1532

■

Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S

devices with 128 or more macrocells

Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see Tables 1 and 2)

5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

PCI-compliant devices available

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V

MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family

Data Sheet or the MAX 7000B Programmable Logic Device Family Data

Sheet.

Table 1. MAX 7000 Device Features

Feature

EPM7032

EPM7064

EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E

Usable

600

1,250

1,800

2,500

3,200

3,750

5,000

gates

Macrocells

128

160

192

256

Logic array

blocks

Maximum

100

104

124

164

user I/O pins

t_PD(ns)

t_SU(ns)

7.5

_FSU(ns)

t_CO1(ns)

_CNT(MHz)

2.5

4.5

125.0

4.5

125.0

151.5

100.0

90.9

Altera Corporation

DS-MAX7000-6.5

12 3 4 5 6 7...62

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