Datasheet > EPM2210F100C4N

EPM2210F100C4N

更新时间： 2024-01-05 05:19:44

品牌	Logo	应用领域
英特尔 - INTEL		LTE 输入元件可编程逻辑
页数	文件大小	规格书
98页	1060K
描述
Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100

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技术参数
数据手册

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EPM2210F100C4N 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	BGA,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.58	其他特性：	IT CAN ALSO OPERATE AT 3.3V
JESD-30 代码：	S-PBGA-B100	JESD-609代码：	e1
专用输入次数：		I/O 线路数量：
端子数量：	100	组织：	0 DEDICATED INPUTS, 0 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	260
可编程逻辑类型：	FLASH PLD	认证状态：	Not Qualified
最大供电电压：	2.625 V	最小供电电压：	2.375 V
标称供电电压：	2.5 V	表面贴装：	YES
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40

EPM2210F100C4N 数据手册

Introduction

For more information on equivalent macrocells, refer to the

MAX II Logic Element to Macrocell Conversion Methodology white

paper.

MAX II devices are available in three speed grades: -3, -4, -5 with -3 being

the fastest. These speed grades represent overall relative performance,

not any specific timing parameter. For propagation delay timing

numbers within each speed grade and density, see the chapter on DC &

Switching Characteristics. Table 1–2 shows MAX II device speed-grade

offerings.

Table 1–2. MAX II Speed Grades

Speed Grade

Device

-3

-4

-5

EPM240

EPM570

EPM1270

EPM2210

MAX II devices are available in space-saving FineLine BGA , Micro

FineLine BGA, and thin quad flat pack (TQFP) packages (see Tables 1–3

and 1–4). MAX II devices support vertical migration within the same

package (e.g., you can migrate between the EPM570, EPM1270, and

EPM2210 devices in the

256-pin FineLine BGA package). Vertical migration means that you can

migrate to devices whose dedicated pins and JTAG pins are the same and

power pins are subsets or supersets for a given package across device

densities. The largest density in any package has the highest number of

power pins; you must layout for the largest planned density in a package

to provide the necessary power pins for migration. For I/O pin migration

across densities, cross reference the available I/O pins using the device

pin-outs for all planned densities of a given package type to identify

which I/O pins can be migrated. The Quartus^®II software can

automatically cross reference and place all pins for you when given a

device migration list.

Altera Corporation

August 2006

Core Version a.b.c variable

1–3

MAX II Device Handbook, Volume 1

1...4 5 678 9 10...98

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与EPM2210F100C4N相关器件

型号	品牌	描述	获取价格	数据表
EPM2210F100I	ALTERA	MAX II Device Family	获取价格
EPM2210F100I3ES	INTEL	Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, FBGA-100	获取价格
EPM2210F100I4N	INTEL	Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100	获取价格
EPM2210F256A3	INTEL	Flash PLD, 7ns, 1700-Cell, CMOS, PBGA256	获取价格
EPM2210F256A3N	ALTERA	Flash PLD, 7ns, 1700-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256	获取价格
EPM2210F256A3N	INTEL	Flash PLD, 7ns, 1700-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256	获取价格