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EP7211-CV-A PDF预览

EP7211-CV-A

更新时间: 2024-11-13 21:54:59
品牌 Logo 应用领域
凌云 - CIRRUS 控制器
页数 文件大小 规格书
166页 2477K
描述
HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211-CV-A 数据手册

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EP7211  
Preliminary Data Sheet  
FEATURES  
High-Performance Ultra-Low-  
Power System-on-Chip with  
LCD Controller  
I Dynamically programmable clock speeds of  
18, 36, 49, and 74 MHz at 2.5 V  
I Performance matching 100-MHz Intel  
Pentium-based PC  
I Socket and register compatible with CL-PS7111  
I Ultra low power  
OVERVIEW  
— Designed for applications that require long battery life  
while using standard AA/AAA batteries or rechargeable  
cells  
— 170 mW at 74 MHz in the Operating State  
— 50 mW at 18 MHz in the Operating State  
— 15 mW in the Idle State (clock to the CPU stopped,  
everything else running)  
— 10 µW in the Standby State (realtime clock ‘on’,  
everything else stopped)  
The EP7211 is designed for ultra-low-power applica-  
tions such as organizers/PDAs, two-way pagers,  
smart cellular phones, and industrial hand-held infor-  
mation appliances. The core-logic functionality of the  
device is built around an ARM720T processor with 8  
kbytes of four-way set-associative unified cache and  
a write buffer. Incorporated into the ARM720T is an  
enhanced memory management unit (MMU), which  
allows for Microsoft Windows CE support.  
I LCD controller  
— Interfaces directly to a single-scan panel monochrome  
LCD  
— Panel width size is programmable from 32 to 1024 pixels  
in 16-pixel increments  
The EP7211 also includes a 32-bit Y2K-compliant  
Real Time Clock (RTC) and comparator.  
— Video frame buffer size programmable up to 128 kbytes  
— Bits per pixel programmable from 1, 2, or 4  
(cont.)  
(cont.)  
Functional Block Diagram  
13-MHZ INPUT  
INTERNAL DATA BUS  
3.6864 MHZ  
PLL  
D0–D31  
ARM720T  
MEMORY CONTROL BLOCK  
CL-PS6700  
32.768-KHZ  
OSCILLATOR  
32.768 KHZ  
ARM7TDMI  
CPU CORE  
PB[0–1], CS[4–5]  
INTFC.  
POR, RUN,  
RESET, WAKEUP  
STATE CONTROL  
EXPCLK, WORD,  
CS[0–3], EXPRDY,  
WRITE  
EXPANSION  
CONTROL  
8-KBYTE  
CACHE  
POWER  
MANAGEMENT  
BATOK, EXTPWR  
PWRFL, BATCHG  
DRAM  
CONTROLLER  
MOE, MWE,  
RAS[0–1], CAS[0–3]  
MMU  
EINT[1–3], FIQ,  
MEDCHG  
INTERRUPT  
CONTROLLER  
WRITE  
BUFFER  
INTERNAL ADDRESS BUS  
A[0–27],  
DRA[0–12]  
FLASHING LED DRIVE  
PORTS A, B, D (8-BIT)  
PORT E (3-BIT)  
KEYBD DRIVERS (0–7)  
BUZZER DRIVE  
RTC  
LCD DMA  
TEST AND  
DEVELOPMENT  
ICE-JTAG  
GPIO  
TIMER  
COUNTERS (2)  
LCD  
CONTROLLER  
DC-TO-DC  
PWM  
LCD DRIVE  
ON-CHIP  
BOOT ROM  
SSI1 (ADC)  
ADCCLK, ADCIN,  
ADCOUT, SMPCLK,  
ADCCS  
ON-CHIP SRAM  
37.5 KBYTES  
LED AND  
PHOTODIODE  
MULTIMEDIA  
CODEC PORT  
IrDA  
ASYNC  
INTERFACE 1  
APB BRIDGE  
EPB BUS  
UART1  
UART2  
SSI2  
SSICLK, SSITXFR,  
SSITXDA, SSIRXDA,  
SSIRSFR  
ASYNC  
INTERFACE 2  
CODEC  
Cirrus Logic, Inc.  
Copyright © Cirrus Logic, Inc. 2001  
(All Rights Reserved)  
DS352PP3  
JUL 2001  
P.O. Box 17847, Austin, Texas 78760  
(512) 445 7222 FAX: (512) 445 7851  
http://www.cirrus.com  
1

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