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EP20K1500CF1020C-7 PDF预览

EP20K1500CF1020C-7

更新时间: 2024-11-07 15:42:39
品牌 Logo 应用领域
阿尔特拉 - ALTERA 输入元件可编程逻辑
页数 文件大小 规格书
90页 1475K
描述
Loadable PLD, 1.4ns, PBGA1020, 33 X 33 MM, 1 MM PITCH, FINE LINE, BGA-1020

EP20K1500CF1020C-7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:HBGA,
针数:1020Reach Compliance Code:compliant
ECCN代码:3A001.A.7.AHTS代码:8542.39.00.01
风险等级:5.78JESD-30 代码:S-PBGA-B1020
JESD-609代码:e1长度:33 mm
湿度敏感等级:3专用输入次数:4
I/O 线路数量:808端子数量:1020
最高工作温度:85 °C最低工作温度:
组织:4 DEDICATED INPUTS, 808 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:HBGA
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
可编程逻辑类型:LOADABLE PLD传播延迟:1.4 ns
认证状态:Not Qualified座面最大高度:3.5 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:33 mm
Base Number Matches:1

EP20K1500CF1020C-7 数据手册

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APEX 20KC  
Programmable Logic  
Device  
®
April 2001, ver. 1.1  
Data Sheet  
Programmable logic device (PLD) manufactured using a 0.15-µm all-  
Features...  
layer copper-metal fabrication process  
25 to 35% faster design performance than APEXTM 20KE devices  
Pin-compatible with APEX 20KE devices  
High-performance, low-power copper interconnect  
MultiCoreTM architecture integrating look-up table (LUT) logic  
and embedded memory  
LUT logic used for register-intensive functions  
Embedded system blocks (ESBs) used to implement memory  
functions, including first-in first-out (FIFO) buffers, dual-port  
RAM, and content-addressable memory (CAM)  
Preliminary  
Information  
High-density architecture  
100,000 to 1.5 million typical gates (see Table 1)  
Up to 51,840 logic elements (LEs)  
Up to 442,368 RAM bits that can be used without reducing  
available logic  
Table 1. APEX 20KC Device Features  
Feature  
Note (1)  
EP20K100C EP20K200C EP20K400C EP20K600C EP20K1000C EP20K1500C  
Maximum  
263,000  
526,000  
1,052,000  
1,537,000  
1,772,000  
2,392,000  
system gates  
Typical gates  
LEs  
100,000  
4,160  
26  
200,000  
8,320  
52  
400,000  
16,640  
104  
600,000  
24,320  
152  
1,000,000  
38,400  
160  
1,500,000  
51,840  
216  
ESBs  
Maximum RAM  
bits  
53,248  
106,496  
212,992  
311,296  
327,680  
442,368  
PLLs (2)  
2
2
4
4
4
4
Speed grades  
-7, -8, -9  
-7, -8, -9  
-7, -8, -9  
-7, -8, -9  
-7, -8, -9  
-7, -8, -9  
(3)  
Maximum  
macrocells  
416  
246  
832  
376  
1,664  
488  
2,432  
588  
2,560  
708  
3,456  
808  
Maximum user  
I/O pins  
Notes:  
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to  
57,000 additional gates.  
(2) PLL: phase-locked loop.  
(3) The -7 speed grade provides the fastest performance.  
Altera Corporation  
1
A-DS-APEX20KC-01.1  

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