Datasheet > EMF20P02V

EMF20P02V

更新时间： 2024-09-16 17:15:43

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
6页	849K
描述
EDFN3X3

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EMF20P02V 数据手册

EMF20P02V

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BVDSS

‐12V

20mΩ

‐18A

RDSON (MAX.)

P‐Channel MOSFET

UIS, Rg 100% Tested

Pb‐Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±8

UNIT

Gate‐Source Voltage

V_GS

T_C= 25 °C

‐18

‐9

Continuous Drain Current

I_D

T_A= 25 °C

T_C= 100 °C

‐12

‐72

Pulsed Drain Current¹

I_DM

T_C= 25 °C

Power Dissipation

P_D

T_C= 100 °C

8.3

2.5

T_A= 25 °C

Power Dissipation

P_D

°C

T_A= 70 °C

1.6

Operating Junction & Storage Temperature Range

T_j, T_stg

‐55 to 150

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

Junction‐to‐Case

Junction‐to‐Ambient³

°C / W

R_JA

¹Pulse width limited by maximum junction temperature.

²Duty cycle  1％

³50°C / W when mounted on a 1 in²pad of 2 oz copper.

2019/6/25

p.1

12 3 4 5 6

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