Datasheet > EM68C08CWAG-25H

EM68C08CWAG-25H

更新时间： 2022-02-26 12:34:35

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
63页	1336K
描述
128M x 8 bit DDRII Synchronous DRAM (SDRAM)

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数据手册

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EM68C08CWAG-25H 数据手册

EtronTech

EM68C08CWAG

 Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS

latency, burst length, burst sequence, test mode, DLL reset, WR, and various vendor specific options to make DDR2

SDRAM useful for various applications.The default value of the mode register is not defined, therefore the mode

LOW on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state of address pins A0 - A13. The DDR2

SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register.The

mode register set command cycle time (t_MRD) is required to complete the write operation to the mode register. The

mode register contents can be changed using the same command and clock cycle requirements during normal

operation as long as all bank are in the precharge state.The mode register is divided into various fields depending on

functionality.

- Burst Length Field (A2, A1, A0): This field specifies the data length of column access and selects the Burst Length.

- Addressing Mode Select Field (A3): The Addressing Mode can be Interleave Mode or Sequential Mode. Both

Sequential Mode and Interleave Mode support burst length of 4 and 8.

- CAS Latency Field (A6, A5, A4): This field specifies the number of clock cycles from the assertion of the Read

command to the first read data. The minimum whole value of CAS Latency

depends on the frequency of CK. The minimum whole value satisfying the following

formula must be programmed into this field. (tCAC(min) ≦ CAS Latency X t_CK)

- Test Mode Field (A7); DLL Reset Mode Field (A8): These two bits must be programmed to "00" in normal operation.

- Write recovery Field (A11, A10, A9): The WR register is used by the DDR2 SDRAM during WRITE with auto

precharge operation. The WR register is used by the DDR2 SDRAM during

WRITE with auto precharge operation.

- (BA0-BA1): Bank addresses to define MRS selection.

Table 5. Mode Register Bitmap

BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field

0^*2

0^*2PD

DLL TM CAS Latency

BT Burst Length Mode Register

A8 DLL Reset

A7 Mode

Burst Type

Sequential

Interleave

A2 A1 A0 BL

Normal

Test

Yes

A12 Active power down exit time Write recovery for autoprecharge^*1

Fast exit (use t_XARD

)

A11

A10

WR(cycles)

A6 A5 A4

CAS Latency

Slow exit (use t_XARDS

)

Reserved

BA1 BA0

MRS Mode

Reserved

EMR(1)

EMR(2)

EMR(3)

NOTE 1: For DDR2-667/800/1066, WR min is determined by t_CK(avg) max and WR max is determined by t_CK(avg) min. WR

[cycles] = RU {t_WR[ns]/t_CK(avg)[ns]}, where RU stands for round up. The mode register must be programmed to this

value.This is also used with t_RPto determine t_DAL

NOTE 2: BA2 and A13 are reserved for future use and must be set to 0 when programming the MR.

Rev. 1.1

Apr. /2016

1...6 7 8910 11 12...63

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与EM68C08CWAG-25H相关器件

型号	品牌	获取价格	描述	数据表
EM68C08CWAG-3H	ETRON	获取价格	128M x 8 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQE-18H	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQE-18IH	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQE-25H	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQE-25IH	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQE-3H	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQE-3IH	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQG-18H	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQG-18IH	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)
EM68C16CWQG-25H	ETRON	获取价格	64M x 16 bit DDRII Synchronous DRAM (SDRAM)

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